This is an automated email from Gerrit. lilvinz ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1474
-- gerrit commit 27eef4685ef024964b701a5e69b28d089ad87bf8 Author: Vincent Kessler <[email protected]> Date: Wed Jul 3 18:21:52 2013 +0200 freertos stacking: fixed alignment and added support for cm4 This fixes: - freertos: detection of padded stack frames by evaluating xPSR This adds: - freertos: support for cm4 - freertos: support for cm4 with fpu enabled Change-Id: I443c46cc9daf993010b9a9aff918c7adff99f02f Signed-off-by: Vincent Kessler <[email protected]> diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c index 04cbdfc..c7931fe 100644 --- a/src/rtos/FreeRTOS.c +++ b/src/rtos/FreeRTOS.c @@ -26,6 +26,8 @@ #include <jtag/jtag.h> #include "target/target.h" #include "target/target_type.h" +#include "target/armv7m.h" +#include "target/cortex_m.h" #include "rtos.h" #include "helper/log.h" #include "helper/types.h" @@ -45,7 +47,12 @@ struct FreeRTOS_params { const unsigned char list_elem_content_offset; const unsigned char thread_stack_offset; const unsigned char thread_name_offset; - const struct rtos_register_stacking *stacking_info; + const struct rtos_register_stacking *stacking_info_cm3; + const struct rtos_register_stacking *stacking_info_cm3_pad; + const struct rtos_register_stacking *stacking_info_cm4f; + const struct rtos_register_stacking *stacking_info_cm4f_pad; + const struct rtos_register_stacking *stacking_info_cm4f_fpu; + const struct rtos_register_stacking *stacking_info_cm4f_fpu_pad; }; const struct FreeRTOS_params FreeRTOS_params_list[] = { @@ -59,7 +66,12 @@ const struct FreeRTOS_params FreeRTOS_params_list[] = { 12, /* list_elem_content_offset */ 0, /* thread_stack_offset; */ 52, /* thread_name_offset; */ - &rtos_standard_Cortex_M3_stacking, /* stacking_info */ + &rtos_standard_Cortex_M3_stacking, /* stacking_m3_info */ + &rtos_standard_Cortex_M3_stacking_pad, /* stacking_m3_info_pad */ + &rtos_standard_Cortex_M4F_stacking, /* stacking_m4f_info */ + &rtos_standard_Cortex_M4F_stacking_pad, /* stacking_m4f_info_pad */ + &rtos_standard_Cortex_M4F_FPU_stacking, /* stacking_m4f_fpu_info */ + &rtos_standard_Cortex_M4F_FPU_stacking_pad, /* stacking_m4f_fpu_info_pad */ }, { "hla_target", /* target_name */ @@ -71,7 +83,12 @@ const struct FreeRTOS_params FreeRTOS_params_list[] = { 12, /* list_elem_content_offset */ 0, /* thread_stack_offset; */ 52, /* thread_name_offset; */ - &rtos_standard_Cortex_M3_stacking, /* stacking_info */ + &rtos_standard_Cortex_M3_stacking, /* stacking_m3_info */ + &rtos_standard_Cortex_M3_stacking_pad, /* stacking_m3_info_pad */ + &rtos_standard_Cortex_M4F_stacking, /* stacking_m4f_info */ + &rtos_standard_Cortex_M4F_stacking_pad, /* stacking_m4f_info_pad */ + &rtos_standard_Cortex_M4F_FPU_stacking, /* stacking_m4f_fpu_info */ + &rtos_standard_Cortex_M4F_FPU_stacking_pad, /* stacking_m4f_fpu_info_pad */ } }; @@ -389,8 +406,96 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, ch LOG_ERROR("Error reading stack frame from FreeRTOS thread"); return retval; } + + /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4F */ + int cm4_fpu_enabled = 0; + struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); + if (is_armv7m(armv7m_target)) { + if (armv7m_target->fp_feature == FPv4_SP) { + /* Found ARM v7m target which includes a FPU */ + uint32_t cpacr; + + retval = target_read_u32(rtos->target, FPU_CPACR, &cpacr); + if (retval != ERROR_OK) { + LOG_ERROR("Could not read CPACR register to check FPU state"); + return -1; + } + + /* Check if CP10 and CP11 are set to full access. */ + if (cpacr & 0x00F00000) { + /* Found target with enabled FPU */ + cm4_fpu_enabled = 1; + } + } + } + + if (cm4_fpu_enabled == 1) { + /* Read the LR to decide between stacking with or without FPU */ + uint32_t LR_svc = 0; + retval = target_read_buffer(rtos->target, + stack_ptr + 0x20, + param->pointer_width, + (uint8_t *)&LR_svc); + if (retval != ERROR_OK) { + LOG_OUTPUT("Error reading stack frame from FreeRTOS thread\r\n"); + return retval; + } + + if ((LR_svc & 0x10) == 0) + { + /* this is a CM4F frame with FPU register set */ + /* Read the xPSR to decide between padding or not */ + uint32_t xPSR = 0; + retval = target_read_buffer(rtos->target, + stack_ptr + 0x80, + param->pointer_width, + (uint8_t *)&xPSR); + if (retval != ERROR_OK) { + LOG_OUTPUT("Error reading stack frame from FreeRTOS thread\r\n"); + return retval; + } + + if (xPSR & 0x200) + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f_fpu_pad, stack_ptr, hex_reg_list); + else + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f_fpu, stack_ptr, hex_reg_list); + } + else + { + /* this is a CM4F frame without FPU register set */ + /* Read the xPSR to decide between padding or not by examining bit 9*/ + uint32_t xPSR = 0; + retval = target_read_buffer(rtos->target, + stack_ptr + 0x40, + param->pointer_width, + (uint8_t *)&xPSR); + if (retval != ERROR_OK) { + LOG_OUTPUT("Error reading stack frame from FreeRTOS thread\r\n"); + return retval; + } + + if (xPSR & 0x200) + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f_pad, stack_ptr, hex_reg_list); + else + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f, stack_ptr, hex_reg_list); + } + } else { + /* Read the xPSR to decide between padding or not */ + uint32_t xPSR = 0; + retval = target_read_buffer(rtos->target, + stack_ptr + 0x3c, + param->pointer_width, + (uint8_t *)&xPSR); + if (retval != ERROR_OK) { + LOG_OUTPUT("Error reading stack frame from FreeRTOS thread\r\n"); + return retval; + } - return rtos_generic_stack_read(rtos->target, param->stacking_info, stack_ptr, hex_reg_list); + if (xPSR & 0x200) + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm3_pad, stack_ptr, hex_reg_list); + else + return rtos_generic_stack_read(rtos->target, param->stacking_info_cm3, stack_ptr, hex_reg_list); + } } static int FreeRTOS_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]) diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c index cb8afd0..377cbc4 100644 --- a/src/rtos/rtos_standard_stackings.c +++ b/src/rtos/rtos_standard_stackings.c @@ -53,6 +53,63 @@ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ { 0x3c, 32 }, /* xPSR */ }; +static const struct stack_register_offset rtos_standard_Cortex_M4F_stack_offsets[] = { + { 0x24, 32 }, /* r0 */ + { 0x28, 32 }, /* r1 */ + { 0x2c, 32 }, /* r2 */ + { 0x30, 32 }, /* r3 */ + { 0x00, 32 }, /* r4 */ + { 0x04, 32 }, /* r5 */ + { 0x08, 32 }, /* r6 */ + { 0x0c, 32 }, /* r7 */ + { 0x10, 32 }, /* r8 */ + { 0x14, 32 }, /* r9 */ + { 0x18, 32 }, /* r10 */ + { 0x1c, 32 }, /* r11 */ + { 0x34, 32 }, /* r12 */ + { -2, 32 }, /* sp */ + { 0x38, 32 }, /* lr */ + { 0x3c, 32 }, /* pc */ + { -1, 96 }, /* FPA1 */ + { -1, 96 }, /* FPA2 */ + { -1, 96 }, /* FPA3 */ + { -1, 96 }, /* FPA4 */ + { -1, 96 }, /* FPA5 */ + { -1, 96 }, /* FPA6 */ + { -1, 96 }, /* FPA7 */ + { -1, 96 }, /* FPA8 */ + { -1, 32 }, /* FPS */ + { 0x40, 32 }, /* xSPR */ +}; + +static const struct stack_register_offset rtos_standard_Cortex_M4F_FPU_stack_offsets[] = { + { 0x64, 32 }, /* r0 */ + { 0x68, 32 }, /* r1 */ + { 0x6c, 32 }, /* r2 */ + { 0x70, 32 }, /* r3 */ + { 0x00, 32 }, /* r4 */ + { 0x04, 32 }, /* r5 */ + { 0x08, 32 }, /* r6 */ + { 0x0c, 32 }, /* r7 */ + { 0x10, 32 }, /* r8 */ + { 0x14, 32 }, /* r9 */ + { 0x18, 32 }, /* r10 */ + { 0x1c, 32 }, /* r11 */ + { 0x74, 32 }, /* r12 */ + { -2, 32 }, /* sp */ + { 0x78, 32 }, /* lr */ + { 0x7c, 32 }, /* pc */ + { -1, 96 }, /* FPA1 */ + { -1, 96 }, /* FPA2 */ + { -1, 96 }, /* FPA3 */ + { -1, 96 }, /* FPA4 */ + { -1, 96 }, /* FPA5 */ + { -1, 96 }, /* FPA6 */ + { -1, 96 }, /* FPA7 */ + { -1, 96 }, /* FPA8 */ + { -1, 32 }, /* FPS */ + { 0x80, 32 }, /* xSPR */ +}; static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = { { 0x08, 32 }, /* r0 (a1) */ @@ -87,15 +144,54 @@ const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = { 0x40, /* stack_registers_size */ -1, /* stack_growth_direction */ 26, /* num_output_registers */ - 8, /* stack_alignment */ + 0, /* stack_alignment */ rtos_standard_Cortex_M3_stack_offsets /* register_offsets */ }; +const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking_pad = { + 0x44, /* stack_registers_size */ + -1, /* stack_growth_direction */ + 26, /* num_output_registers */ + 0, /* stack_alignment */ + rtos_standard_Cortex_M3_stack_offsets /* register_offsets */ +}; + +const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking = { + 0x44, /* stack_registers_size, ignore the additional 16 fpu registers */ + -1, /* stack_growth_direction */ + 26, /* num_output_registers */ + 0, /* stack_alignment */ + rtos_standard_Cortex_M4F_stack_offsets /* register_offsets */ +}; + +const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking_pad = { + 0x48, /* stack_registers_size, ignore the additional 16 fpu registers */ + -1, /* stack_growth_direction */ + 26, /* num_output_registers */ + 0, /* stack_alignment */ + rtos_standard_Cortex_M4F_stack_offsets /* register_offsets */ +}; + +const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking = { + 0xcc, /* stack_registers_size, ignore the additional 16 fpu registers */ + -1, /* stack_growth_direction */ + 26, /* num_output_registers */ + 0, /* stack_alignment */ + rtos_standard_Cortex_M4F_FPU_stack_offsets /* register_offsets */ +}; + +const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking_pad = { + 0xd0, /* stack_registers_size, ignore the additional 16 fpu registers */ + -1, /* stack_growth_direction */ + 26, /* num_output_registers */ + 0, /* stack_alignment */ + rtos_standard_Cortex_M4F_FPU_stack_offsets /* register_offsets */ +}; const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = { 0x48, /* stack_registers_size */ -1, /* stack_growth_direction */ 26, /* num_output_registers */ - 8, /* stack_alignment */ + 0, /* stack_alignment */ rtos_standard_Cortex_R4_stack_offsets /* register_offsets */ }; diff --git a/src/rtos/rtos_standard_stackings.h b/src/rtos/rtos_standard_stackings.h index aa54820..a77a374 100644 --- a/src/rtos/rtos_standard_stackings.h +++ b/src/rtos/rtos_standard_stackings.h @@ -28,6 +28,11 @@ #include "rtos.h" extern const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking; +extern const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking_pad; +extern const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking; +extern const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking_pad; +extern const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking; +extern const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking_pad; extern const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking; #endif /* ifndef INCLUDED_RTOS_STANDARD_STACKINGS_H_ */ -- ------------------------------------------------------------------------------ This SF.net email is sponsored by Windows: Build for Windows Store. http://p.sf.net/sfu/windows-dev2dev _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
