This is an automated email from Gerrit.

Spencer Oliver ([email protected]) just uploaded a new patch set to Gerrit, 
which you can find at http://openocd.zylin.com/1539

-- gerrit

commit 45cd9b637073ac6a0bc3a3b8ae1ba5abcf4a040e
Author: Spencer Oliver <[email protected]>
Date:   Mon Aug 5 17:46:09 2013 +0100

    armv7m: use consistent arm.cpsr member
    
    We already set cpsr in armv7m_build_reg_cache, so lets use it for all other
    accesses to this field.
    
    Change-Id: I19b3b21ecf1571bbea12e1be664845e6544f6fa1
    Signed-off-by: Spencer Oliver <[email protected]>

diff --git a/src/target/arm.h b/src/target/arm.h
index 4a4d928..528fd2f 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -97,7 +97,7 @@ struct arm {
        /** Handle to the PC; valid in all core modes. */
        struct reg *pc;
 
-       /** Handle to the CPSR; valid in all core modes. */
+       /** Handle to the CPSR/xPSR; valid in all core modes. */
        struct reg *cpsr;
 
        /** Handle to the SPSR; valid only in core modes with an SPSR. */
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 1d08c95..fbe635b 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -430,7 +430,7 @@ static int cortex_m3_debug_entry(struct target *target)
                        arm->read_core_reg(target, r, i, ARM_MODE_ANY);
        }
 
-       r = arm->core_cache->reg_list + ARMV7M_xPSR;
+       r = arm->cpsr;
        xPSR = buf_get_u32(r->value, 0, 32);
 
 #ifdef ARMV7_GDB_HACKS
@@ -732,7 +732,7 @@ static int cortex_m3_resume(struct target *target, int 
current,
                r->valid = true;
 
                /* Make sure we are in Thumb mode */
-               r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR;
+               r = armv7m->arm.cpsr;
                buf_set_u32(r->value, 24, 1, 1);
                r->dirty = true;
                r->valid = true;
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 5d31c7a..05114b8 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -427,7 +427,7 @@ static int adapter_debug_entry(struct target *target)
        /* make sure we clear the vector catch bit */
        adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
 
-       r = arm->core_cache->reg_list + ARMV7M_xPSR;
+       r = arm->cpsr;
        xPSR = buf_get_u32(r->value, 0, 32);
 
        /* Are we in an exception handler */

-- 

------------------------------------------------------------------------------
Get your SQL database under version control now!
Version control is standard for application code, but databases havent 
caught up. So what steps can you take to put your SQL databases under 
version control? Why should you start doing it? Read more to find out.
http://pubads.g.doubleclick.net/gampad/clk?id=49501711&iu=/4140/ostg.clktrk
_______________________________________________
OpenOCD-devel mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/openocd-devel

Reply via email to