Hi All,
Has anyone used openocd on the Marvell ARAMADA 370 SoC?
I have a Globalscale Mirabox and am trying to get JTAG debugging working
on it. I am using an Amontec jtagkey, and have some basic functionality
working. But I can't access the bus in any way without getting errors
like this:
> arm disassemble 0x0063C9A0 10
JTAG-DP STICKY ERROR
MEM_AP_CSW 0x28000d2, MEM_AP_TAR 0x63c9a0
JTAG-DP STICKY ERROR
MEM_AP_CSW 0x28000d2, MEM_AP_TAR 0x63c9a0
Block read error address 0x63c9a0
in procedure 'arm'
I can halt the cpu, single step, set breakpoints and run to it.
I can dump the registers and get (what looks like) good values.
But just can't access anything on the bus.
It is a really simple config at this point:
jtag newtap armada370 dap -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id 0x4ba00477
target create armada370.cpu cortex_a8 -chain-position armada370.dap
proc armada370_dbginit {target} {
cortex_a dbginit
}
armada370.cpu configure -event reset-assert-post "armada370_dbginit
armada370.cpu"
On startup I get:
Open On-Chip Debugger 0.7.0 (2013-08-13-15:01)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
trst_and_srst separate srst_gates_jtag trst_push_pull
srst_open_drain connect_deassert_srst
adapter_nsrst_delay: 200
jtag_ntrst_delay: 200
adapter speed: 1000 kHz
Info : clock speed 1000 kHz
Info : JTAG tap: armada370.dap tap/device found: 0x4ba00477 (mfg:
0x23b, part: 0xba00, ver: 0x4)
Info : armada370.cpu: hardware has 6 breakpoints, 2 watchpoints
Info : number of cache level 1
Error: mpdir not in multiprocessor format
dap info 1 reports:
AP ID register 0x24770002
Type is MEM-AP APB
AP BASE 0xc2300000
ROM table in legacy format
MEMTYPE System memory not present. Dedicated debug bus.
ROMTABLE[0x0] = 0x1003
Component base address 0xc2301000,start address 0xc2301000
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
Peripheral ID[4..0] = hex 03 00 0e 9c 08
Part is Cortex-A8 Debug (Debug Unit)
ROMTABLE[0x4] = 0x2003
Component base address 0xc2302000,start address 0xc2302000
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
Peripheral ID[4..0] = hex 03 00 0e 99 21
Part is Cortex-A8 ETM (Embedded Trace)
ROMTABLE[0x8] = 0x3003
Component base address 0xc2303000,start address 0xc2303000
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
Peripheral ID[4..0] = hex 03 00 0e 99 06
Part is Coresight CTI (Cross Trigger)
ROMTABLE[0xc] = 0x4003
Component base address 0xc2304000,start address 0xc2304000
Component class is 0x9, CoreSight component
Type is 0x21, Trace Sink, Buffer
Peripheral ID[4..0] = hex 04 00 3b b9 07
Part is Coresight ETB (Trace Buffer)
ROMTABLE[0x10] = 0x5003
Component base address 0xc2305000,start address 0xc2305000
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
Peripheral ID[4..0] = hex 04 00 3b b9 06
Part is Coresight CTI (Cross Trigger)
ROMTABLE[0x14] = 0x0
End of ROM table
After googling around I saw suggestions to vary the clocking speeds.
A lot of various adapter_khz and "dap memaccess" values didn't seem to
make any difference.
Anyone have any ideas?
Regards
Greg
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