Hi, As Freddie Chopin already reported, dual-core LPC microcontrollers do not work properly. It was also discussed on IRC with some user I do not remember the name of.
First time SRST is pulled in jtag_init_reset(). Second time it's pulled from ocd_process_reset_inner Tcl procedure. It also doesn't seem to respect srst_assert_width and srts_assert_delay (I'm not sure here). And it's known to break multi-chain operation on those LPC parts (the M0 core freaks out). Some targets also override init_reset to do additional things. Other reset-related issues I'm aware of: 1. http://openocd.zylin.com/1516 without this change it's impossible to put MSP430 into JTAG mode, that's needed if you have it in the chain with some other supported target. Unfortunately, this is not enough as MSP430 needs the magic sequence to be done faster than what we can get this way. http://openocd.zylin.com/#/c/1550/ this was supposed to solve, and is known to work on real hardware. Andreas, what do you propose instead? 2. Anything else I'm forgetting about? I'm not sure how to not forget about all the stuff, apparently, OpenOCD project lacks any well-established procedures to work with the bug tracker. -- Be free, use free (http://www.gnu.org/philosophy/free-sw.html) software! mailto:[email protected] ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60135031&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
