This is an automated email from Gerrit. Spencer Oliver ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1727
-- gerrit commit 9bf77cca32b969a2d219b0f9e99af9b2220c6a40 Author: Spencer Oliver <[email protected]> Date: Wed Oct 23 22:19:13 2013 +0100 build: remove unnecessary casting Some functions were still casting buf_get_u32 and buf_set_u32 to (uint8_t *) even though it now takes a (void *). Change-Id: Idfcdd9c948bed9a413d435abb0293705d61db0fd Signed-off-by: Spencer Oliver <[email protected]> diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c index 4244ba2..bfa301b 100644 --- a/src/flash/nor/stm32f1x.c +++ b/src/flash/nor/stm32f1x.c @@ -1313,10 +1313,10 @@ COMMAND_HANDLER(stm32x_handle_options_read_command) int user_data = optionbyte; - if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1)) + if (buf_get_u32(&optionbyte, OPT_ERROR, 1)) command_print(CMD_CTX, "Option Byte Complement Error"); - if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1)) + if (buf_get_u32(&optionbyte, OPT_READOUT, 1)) command_print(CMD_CTX, "Readout Protection On"); else command_print(CMD_CTX, "Readout Protection Off"); @@ -1324,23 +1324,23 @@ COMMAND_HANDLER(stm32x_handle_options_read_command) /* user option bytes are offset depending on variant */ optionbyte >>= stm32x_info->option_offset; - if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1)) + if (buf_get_u32(&optionbyte, OPT_RDWDGSW, 1)) command_print(CMD_CTX, "Software Watchdog"); else command_print(CMD_CTX, "Hardware Watchdog"); - if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1)) + if (buf_get_u32(&optionbyte, OPT_RDRSTSTOP, 1)) command_print(CMD_CTX, "Stop: No reset generated"); else command_print(CMD_CTX, "Stop: Reset generated"); - if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1)) + if (buf_get_u32(&optionbyte, OPT_RDRSTSTDBY, 1)) command_print(CMD_CTX, "Standby: No reset generated"); else command_print(CMD_CTX, "Standby: Reset generated"); if (stm32x_info->has_dual_banks) { - if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1)) + if (buf_get_u32(&optionbyte, OPT_BFB2, 1)) command_print(CMD_CTX, "Boot: Bank 0"); else command_print(CMD_CTX, "Boot: Bank 1"); diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index daa37ba..a89b0fd 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1486,19 +1486,19 @@ static int cortex_m3_load_core_reg_u32(struct target *target, switch (num) { case ARMV7M_PRIMASK: - *value = buf_get_u32((uint8_t *)value, 0, 1); + *value = buf_get_u32(value, 0, 1); break; case ARMV7M_BASEPRI: - *value = buf_get_u32((uint8_t *)value, 8, 8); + *value = buf_get_u32(value, 8, 8); break; case ARMV7M_FAULTMASK: - *value = buf_get_u32((uint8_t *)value, 16, 1); + *value = buf_get_u32(value, 16, 1); break; case ARMV7M_CONTROL: - *value = buf_get_u32((uint8_t *)value, 24, 2); + *value = buf_get_u32(value, 24, 2); break; } @@ -1550,19 +1550,19 @@ static int cortex_m3_store_core_reg_u32(struct target *target, switch (num) { case ARMV7M_PRIMASK: - buf_set_u32((uint8_t *)®, 0, 1, value); + buf_set_u32(®, 0, 1, value); break; case ARMV7M_BASEPRI: - buf_set_u32((uint8_t *)®, 8, 8, value); + buf_set_u32(®, 8, 8, value); break; case ARMV7M_FAULTMASK: - buf_set_u32((uint8_t *)®, 16, 1, value); + buf_set_u32(®, 16, 1, value); break; case ARMV7M_CONTROL: - buf_set_u32((uint8_t *)®, 24, 2, value); + buf_set_u32(®, 24, 2, value); break; } diff --git a/src/target/etm.c b/src/target/etm.c index be5dd02..42b0ec1 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -318,7 +318,7 @@ struct reg_cache *etm_build_reg_cache(struct target *target, etm_core, 1); etm_get_reg(reg_list); - etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32); + etm_ctx->config = buf_get_u32(&arch_info->value, 0, 32); config = etm_ctx->config; /* figure ETM version then add base registers */ diff --git a/src/target/hla_target.c b/src/target/hla_target.c index ee99e08..1361e0d 100644 --- a/src/target/hla_target.c +++ b/src/target/hla_target.c @@ -120,19 +120,19 @@ static int adapter_load_core_reg_u32(struct target *target, switch (num) { case ARMV7M_PRIMASK: - *value = buf_get_u32((uint8_t *) value, 0, 1); + *value = buf_get_u32(value, 0, 1); break; case ARMV7M_BASEPRI: - *value = buf_get_u32((uint8_t *) value, 8, 8); + *value = buf_get_u32(value, 8, 8); break; case ARMV7M_FAULTMASK: - *value = buf_get_u32((uint8_t *) value, 16, 1); + *value = buf_get_u32(value, 16, 1); break; case ARMV7M_CONTROL: - *value = buf_get_u32((uint8_t *) value, 24, 2); + *value = buf_get_u32(value, 24, 2); break; } @@ -218,19 +218,19 @@ static int adapter_store_core_reg_u32(struct target *target, switch (num) { case ARMV7M_PRIMASK: - buf_set_u32((uint8_t *) ®, 0, 1, value); + buf_set_u32(®, 0, 1, value); break; case ARMV7M_BASEPRI: - buf_set_u32((uint8_t *) ®, 8, 8, value); + buf_set_u32(®, 8, 8, value); break; case ARMV7M_FAULTMASK: - buf_set_u32((uint8_t *) ®, 16, 1, value); + buf_set_u32(®, 16, 1, value); break; case ARMV7M_CONTROL: - buf_set_u32((uint8_t *) ®, 24, 2, value); + buf_set_u32(®, 24, 2, value); break; } diff --git a/src/target/xscale.c b/src/target/xscale.c index 388c8eb..7e6c8f8 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -337,7 +337,7 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words } for (i = 0; i < num_words; i++) - *(buffer++) = buf_get_u32((uint8_t *)&field1[i], 0, 32); + *(buffer++) = buf_get_u32(&field1[i], 0, 32); free(field1); -- ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60135991&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
