2013/7/9 <[email protected]>: > This is an automated email from Gerrit. > > Brad Riensche ([email protected]) just uploaded a new patch set to > Gerrit, which you can find at http://openocd.zylin.com/1494 > > -- gerrit > > commit 04cc505d409e9c159f216a96fe2b61907c4374dd > Author: Brad Riensche <[email protected]> > Date: Tue Jul 9 16:28:14 2013 -0500 > > Add tcl configurations for Altera Soc devices > > This commit adds two tcl configuration files, one for the Altera > Cyclone V SoC series, and one for the SoCkit development board. > The board configuration is able to halt and resume the cpu cores, > and dump register contents etc. It has not been fully tested, however. > > Change-Id: Id3f18c3408975cf986a5f5aec410b5b13240c35e > Signed-off-by: Brad Riensche <[email protected]> > > diff --git a/tcl/board/altera_sockit.cfg b/tcl/board/altera_sockit.cfg > new file mode 100644 > index 0000000..5694143 > --- /dev/null > +++ b/tcl/board/altera_sockit.cfg > @@ -0,0 +1,19 @@ > +# > +# Cyclone V SocKit board > +# http://www.altera.com/b/arrow-sockit.html > +# > +# Software support page: > +# http://www.rocketboards.org/ > + > +# openocd does not currently support the on-board USB Blaster II. > +# Install the JTAG header and use a USB Blaster instead. > +interface usb_blaster > + > +source [find target/altera_fpgasoc.cfg] > + > +# If the USB Blaster II were supported, these settings would be needed > +#usb_blaster_vid_pid 0x6810 0x09fb > +#usb_blaster_device_desc "USB-Blaster II" > + > +adapter_khz 100 > + > diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg > new file mode 100644 > index 0000000..9c7b419 > --- /dev/null > +++ b/tcl/target/altera_fpgasoc.cfg > @@ -0,0 +1,64 @@ > +# > +# Altera cyclone V SoC family, 5Cxxx > +# > +if { [info exists CHIPNAME] } { > + set _CHIPNAME $CHIPNAME > +} else { > + set _CHIPNAME fpgasoc > +} > + > +# CoreSight Debug Access Port > +if { [info exists DAP_TAPID] } { > + set _DAP_TAPID $DAP_TAPID > +} else { > + set _DAP_TAPID 0x4ba00477 > +} > + > +jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ > + -expected-id $_DAP_TAPID > + > +# Subsidiary TAP: fpga > +if { [info exists FPGA_TAPID] } { > + set _FPGA_TAPID $FPGA_TAPID > +} else { > + set _FPGA_TAPID 0x02d020dd > +} > +jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 > -expected-id $_FPGA_TAPID > + > + > +# > +# Cortex A9 target > +# > + > +# GDB target: Cortex-A9, using DAP, configuring only one core > +# Base addresses of cores: > +# core 0 - 0x80110000 > +# core 1 - 0x80112000 > + > +# Slow speed to be sure it will work > +jtag_rclk 1000 > + > +set _TARGETNAME1 $_CHIPNAME.cpu.0 > +set _TARGETNAME2 $_CHIPNAME.cpu.1 > + > +# A9 core 0 > +target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \ > + -coreid 0 -dbgbase 0x80110000 > + > +$_TARGETNAME1 configure -event reset-start { jtag_rclk 1000 } > +$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1" > +$_TARGETNAME1 configure -event gdb-attach { halt } > + > + > +# A9 core 1 > +#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \ > +# -coreid 1 -dbgbase 0x80112000 > + > +#$_TARGETNAME2 configure -event reset-start { jtag_rclk 1000 } > +#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit > $_TARGETNAME2" > +#$_TARGETNAME2 configure -event gdb-attach { halt } > + > +proc cycv_dbginit {target} { > + # General Cortex A8/A9 debug initialisation > + cortex_a8 dbginit > +} > > -- > > ------------------------------------------------------------------------------ > See everything from the browser to the database with AppDynamics > Get end-to-end visibility with application monitoring from AppDynamics > Isolate bottlenecks and diagnose root cause in seconds. > Start your free trial of AppDynamics Pro today! > http://pubads.g.doubleclick.net/gampad/clk?id=48808831&iu=/4140/ostg.clktrk > _______________________________________________ > OpenOCD-devel mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/openocd-devel
Hello Brad, How far did you test this configuration file ? I have implemented an USB-Blaster II driver (http://openocd.zylin.com/#/c/1791/) but I can't make it works with your config. I did test my driver with an OpenRISC softcore in the FPGA and it works fine. This is what I get: Info : 218 97 core.c:951 jtag_examine_chain_display(): JTAG tap: fpgasoc.dap tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4) Info : 219 97 core.c:951 jtag_examine_chain_display(): JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e, part: 0x2d02, ver: 0x0) Debug: 220 97 core.c:1208 jtag_validate_ircapture(): IR capture validation scan Debug: 221 110 core.c:1265 jtag_validate_ircapture(): fpgasoc.dap: IR capture 0x01 Debug: 222 110 core.c:1265 jtag_validate_ircapture(): fpgasoc.fpga.tap: IR capture 0x155 Debug: 223 111 openocd.c:145 handle_init_command(): Examining targets... Debug: 224 111 target.c:1361 target_call_event_callbacks(): target event 21 (examine-start) Debug: 225 111 arm_adi_v5.c:806 ahbap_debugport_init(): Debug: 226 158 arm_adi_v5.c:768 dap_syssec(): DAP: mdmap_init for idcode: 4ba00477 Debug: 227 210 arm_adi_v5.c:665 dap_syssec_kinetis_mdmap(): id doesn't match 24770002 != 0x001C0000 Debug: 228 257 adi_v5_jtag.c:271 jtagdp_transaction_endcheck(): jtag-dp: CTRL/STAT error, 0xf0000003 Debug: 229 257 adi_v5_jtag.c:291 jtagdp_transaction_endcheck(): MEM-AP Cached values: ap_bank 0x0, ap_csw 0xa2000020, ap_tar 0x0 Error: 230 257 adi_v5_jtag.c:295 jtagdp_transaction_endcheck(): JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed Debug: 231 278 adi_v5_jtag.c:315 jtagdp_transaction_endcheck(): jtag-dp: CTRL/STAT 0xf0000001 Error: 232 324 adi_v5_jtag.c:331 jtagdp_transaction_endcheck(): MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0 Debug: 233 324 openocd.c:147 handle_init_command(): target examination failed I don't have my USB-Blaster right now to test your configuration file. I'll do that tomorrow. Franck. ------------------------------------------------------------------------------ November Webinars for C, C++, Fortran Developers Accelerate application performance with scalable programming models. Explore techniques for threading, error checking, porting, and tuning. Get the most from the latest Intel processors and coprocessors. See abstracts and register http://pubads.g.doubleclick.net/gampad/clk?id=60136231&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
