This is an automated email from Gerrit. Oleksij Rempel ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1932
-- gerrit commit fe94847c9759ebb891d2d96ba21938419b67a92c Author: Oleksij Rempel <[email protected]> Date: Wed Jan 22 12:21:48 2014 +0100 mips32.c: cache debug caps and support EJTAG 2.0 specific changes EJTAG v2.0 indicated some debug caps in IMP register. V2.6 moved them to DCR register. To make it more universal, convert this values and store them for later use. Change-Id: Id6b9f47c9c2ea94d37281ebfcae5acf357261ddf Signed-off-by: Oleksij Rempel <[email protected]> diff --git a/src/target/mips32.c b/src/target/mips32.c index a2e4db1..ea07082 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -540,31 +540,36 @@ int mips32_configure_break_unit(struct target *target) if (retval != ERROR_OK) return retval; - /* EJTAG 2.0 set IB and DB bits in IMP instead of DCR. - * Since this DCR bits should be reseved on DCR 2.0, we can - * just remap them. */ + /* EJTAG 2.0 set IB and DB bits in IMP instead of DCR. */ if (ejtag_info->ejtag_version == EJTAG_VERSION_20) { + ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM; if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB)) - dcr |= EJTAG_DCR_IB; + ejtag_info->debug_caps |= EJTAG_DCR_IB; if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB)) - dcr |= EJTAG_DCR_DB; - } + ejtag_info->debug_caps |= EJTAG_DCR_DB; + } else + /* keep debug caps for later use */ + ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM + | EJTAG_DCR_IB | EJTAG_DCR_DB); + - if (dcr & EJTAG_DCR_IB) { + if (ejtag_info->debug_caps & EJTAG_DCR_IB) { retval = mips32_configure_ibs(target); if (retval != ERROR_OK) return retval; } - if (dcr & EJTAG_DCR_DB) { + if (ejtag_info->debug_caps & EJTAG_DCR_DB) { retval = mips32_configure_dbs(target); if (retval != ERROR_OK) return retval; } /* check if target endianness settings matches debug control register */ - if (((dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) || - (!(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN))) + if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) + && (target->endianness == TARGET_LITTLE_ENDIAN)) || + (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) + && (target->endianness == TARGET_BIG_ENDIAN))) LOG_WARNING("DCR endianness settings does not match target settings"); LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h index ba3470d..9d676f6 100644 --- a/src/target/mips_ejtag.h +++ b/src/target/mips_ejtag.h @@ -189,6 +189,7 @@ struct mips_ejtag { /* Memory-Mapped Registers. This addresses are not same on different * EJTAG versions. */ + uint32_t debug_caps; uint32_t ejtag_ibs_addr; /* Instruction Address Break Status */ uint32_t ejtag_iba0_addr; /* IAB channel 0 */ uint32_t ejtag_ibc_offs; /* IAB Control offset */ -- ------------------------------------------------------------------------------ Managing the Performance of Cloud-Based Applications Take advantage of what the Cloud has to offer - Avoid Common Pitfalls. Read the Whitepaper. http://pubads.g.doubleclick.net/gampad/clk?id=121051231&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
