This is an automated email from Gerrit. Ivan Sergeev ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1960
-- gerrit commit a88cef272140b25bd57e374e07d4a56895099bcf Author: Vanya Sergeev <[email protected]> Date: Thu Feb 20 01:06:04 2014 -0800 cfg: refactor lpc1xxx targets onto one base config Change-Id: If0cbc37985abf17ef7c1f7d0688e76500fac228f Signed-off-by: Vanya Sergeev <[email protected]> diff --git a/tcl/board/mbed-lpc11u24.cfg b/tcl/board/mbed-lpc11u24.cfg index 6a58264..40c8bd5 100644 --- a/tcl/board/mbed-lpc11u24.cfg +++ b/tcl/board/mbed-lpc11u24.cfg @@ -4,10 +4,15 @@ source [find interface/cmsis-dap.cfg] -# increase working area to 8KB -set WORKAREASIZE 0x2000 - -# chip name +# NXP LPC11U24 Cortex-M0 with 32kB Flash and 8kB SRAM set CHIPNAME lpc11u24 +set CHIPSERIES lpc1100 +set CPUTAPID 0x0bb11477 +set CPUROMSIZE 0x8000 +set CPURAMSIZE 0x2000 + +# After reset the chip is clocked by the ~12MHz internal RC oscillator. +# CCLK is the core clock frequency in KHz +set CCLK 12000 -source [find target/lpc11uxx.cfg] +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1114.cfg b/tcl/target/lpc1114.cfg index fe14edc..8eacd71 100644 --- a/tcl/target/lpc1114.cfg +++ b/tcl/target/lpc1114.cfg @@ -1,7 +1,12 @@ # NXP LPC1114 Cortex-M0 set CHIPNAME lpc1114 +set CHIPSERIES lpc1100 set CPUTAPID 0x0bb11477 +# After reset the chip is clocked by the ~12MHz internal RC oscillator. +# CCLK is the core clock frequency in KHz +set CCLK 12000 + if { ![info exists CPUROMSIZE] } { error "CPUROMSIZE is not set. The LPC1114 part is available in many Flash and RAM size configurations. Please set CPUROMSIZE before including this configuration file." } @@ -9,13 +14,4 @@ if { ![info exists CPURAMSIZE] } { error "CPURAMSIZE is not set. The LPC1114 part is available in many Flash and RAM size configurations. Please set CPURAMSIZE before including this configuration file." } -# After reset the chip is clocked by the ~12MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# -# CCLK is the core clock frequency in KHz -set CCLK 12000 - -source [find lpc11xx.cfg] +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc11uxx.cfg b/tcl/target/lpc11uxx.cfg deleted file mode 100644 index 6968fcd..0000000 --- a/tcl/target/lpc11uxx.cfg +++ /dev/null @@ -1,48 +0,0 @@ -# -# NXP lpc11uxx family - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc11uxx -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 6kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x1800 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x00000000 -} - -# delays on reset lines -adapter_nsrst_delay 100 -#jtag_ntrst_delay 100 - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -#set _FLASHNAME $_CHIPNAME.flash -#flash bank $_FLASHNAME lpc2000 0 0 0 0 $_TARGETNAME - -# if srst is not fitted use SYSRESETREQ to -# perform a soft reset -cortex_m reset_config sysresetreq diff --git a/tcl/target/lpc11xx.cfg b/tcl/target/lpc11xx.cfg deleted file mode 100644 index 3879b07..0000000 --- a/tcl/target/lpc11xx.cfg +++ /dev/null @@ -1,101 +0,0 @@ -# Main file for NXP LPC11xx Cortex-M0 -# -# !!!!!! -# -# This file should not be included directly, rather -# by the lpc1112.cfg, lpc1114.cfg, etc. which set the -# needed variables to the appropriate values. -# -# !!!!!! - -# LPC11xx chips support only SWD transports. -# Source swj-dp for generic swj_newdap. -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - error "_CHIPNAME not set. Please do not include lpc11xx.cfg directly, but the specific chip configuration file (lpc1112.cfg, lpc1114.cfg, etc)." -} - -# After reset the chip is clocked by the ~12MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# -# CCLK is the core clock frequency in KHz -if { [info exists CCLK] } { - set _CCLK $CCLK -} else { - set _CCLK 12000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - error "_CPUTAPID not set. Please do not include lpc11xx.cfg directly, but the specific chip configuration file (lpc1112.cfg, lpc1114.cfg, etc)." -} - -if { [info exists CPURAMSIZE] } { - set _CPURAMSIZE $CPURAMSIZE -} else { - error "_CPURAMSIZE not set. Please do not include lpc11xx.cfg directly, but the specific chip configuration file (lpc1112.cfg, lpc1114.cfg, etc)." -} - -if { [info exists CPUROMSIZE] } { - set _CPUROMSIZE $CPUROMSIZE -} else { - error "_CPUROMSIZE not set. Please do not include lpc11xx.cfg directly, but the specific chip configuration file (lpc1112.cfg, lpc1114.cfg, etc)." -} - -if { [info exists TRANSPORT] } { - set _TRANSPORT $TRANSPORT -} else { - # Default to the SWD transport used by ST-Link v2. - set _TRANSPORT hla_swd -} - -transport select $_TRANSPORT - -if { $_TRANSPORT == "hla_swd" } { - hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID - set _TARGETTYPE hla_target -} else { - swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - set _TARGETTYPE cortex_m -} - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME $_TARGETTYPE -chain-position $_TARGETNAME - -# The LPC11xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) -$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE - -# The LPC11xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code -# (including a boot loader which verifies the flash exception table's checksum). -# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ - lpc1700 $_CCLK calc_checksum - -$_TARGETNAME configure -event reset-init { - # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select - # "User Flash Mode" where interrupt vectors are _not_ remapped, - # and reside in flash instead). - # - # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description - # Bit Symbol Value Description - # 1:0 MAP System memory remap - # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. - # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. - # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. - # 31:2 - - Reserved. - - mww 0x40048000 0x02 -} - -# FIXME LPC11xx supports SYSRESETREQ, but this reset configuration option is -# only available under the cortex_m target at the moment, not the hla_target -# target. -#cortex_m reset_config sysresetreq diff --git a/tcl/target/lpc1751.cfg b/tcl/target/lpc1751.cfg index 28edddb..8d6aade 100644 --- a/tcl/target/lpc1751.cfg +++ b/tcl/target/lpc1751.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM, +# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB SRAM set CHIPNAME lpc1751 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x2000 set CPUROMSIZE 0x8000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1752.cfg b/tcl/target/lpc1752.cfg index 3aae38f..1106e98 100644 --- a/tcl/target/lpc1752.cfg +++ b/tcl/target/lpc1752.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1752 Cortex-M3 with 64kB Flash and 16kB Local On-Chip SRAM, +# NXP LPC1752 Cortex-M3 with 64kB Flash and 16kB SRAM set CHIPNAME lpc1752 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x4000 set CPUROMSIZE 0x10000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1754.cfg b/tcl/target/lpc1754.cfg index ae2ad50..762459e 100644 --- a/tcl/target/lpc1754.cfg +++ b/tcl/target/lpc1754.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM, +# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB SRAM set CHIPNAME lpc1754 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x4000 set CPUROMSIZE 0x20000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1756.cfg b/tcl/target/lpc1756.cfg index 8110727..1540b80 100644 --- a/tcl/target/lpc1756.cfg +++ b/tcl/target/lpc1756.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB SRAM set CHIPNAME lpc1756 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x40000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1758.cfg b/tcl/target/lpc1758.cfg index 79f6624..b67229a 100644 --- a/tcl/target/lpc1758.cfg +++ b/tcl/target/lpc1758.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1758 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +# NXP LPC1758 Cortex-M3 with 512kB Flash and 32kB+32kB SRAM set CHIPNAME lpc1758 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x80000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1759.cfg b/tcl/target/lpc1759.cfg index 3560e97..124c17d 100644 --- a/tcl/target/lpc1759.cfg +++ b/tcl/target/lpc1759.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1759 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +# NXP LPC1759 Cortex-M3 with 512kB Flash and 32kB+32kB SRAM set CHIPNAME lpc1759 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x80000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1763.cfg b/tcl/target/lpc1763.cfg index 08a2be3..b3dcf32 100644 --- a/tcl/target/lpc1763.cfg +++ b/tcl/target/lpc1763.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1763 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM, +# NXP LPC1763 Cortex-M3 with 256kB Flash and 32kB+32kB SRAM set CHIPNAME lpc1763 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x40000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1764.cfg b/tcl/target/lpc1764.cfg index df7ab93..2813061 100644 --- a/tcl/target/lpc1764.cfg +++ b/tcl/target/lpc1764.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1764 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +# NXP LPC1764 Cortex-M3 with 256kB Flash and 16kB+16kB SRAM set CHIPNAME lpc1764 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x4000 set CPUROMSIZE 0x20000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1765.cfg b/tcl/target/lpc1765.cfg index 6d8e8ea..674e23c 100644 --- a/tcl/target/lpc1765.cfg +++ b/tcl/target/lpc1765.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+1632kB Local On-Chip SRAM, +# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+32kB SRAM set CHIPNAME lpc1765 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x40000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1766.cfg b/tcl/target/lpc1766.cfg index 8956c06..9e6195c 100644 --- a/tcl/target/lpc1766.cfg +++ b/tcl/target/lpc1766.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1766 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +# NXP LPC1766 Cortex-M3 with 256kB Flash and 16kB+16kB SRAM set CHIPNAME lpc1766 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x40000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1767.cfg b/tcl/target/lpc1767.cfg index 825dbeb..b6b9f81 100644 --- a/tcl/target/lpc1767.cfg +++ b/tcl/target/lpc1767.cfg @@ -2,20 +2,15 @@ # ! UNTESTED ! # !!!!!!!!!!!! -# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB SRAM set CHIPNAME lpc1767 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x80000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg index a436b30..7310da2 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -1,17 +1,12 @@ -# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB SRAM set CHIPNAME lpc1768 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x80000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1769.cfg b/tcl/target/lpc1769.cfg index 61ab3ee..53aa5b3 100644 --- a/tcl/target/lpc1769.cfg +++ b/tcl/target/lpc1769.cfg @@ -1,17 +1,12 @@ -# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB SRAM set CHIPNAME lpc1769 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x8000 set CPUROMSIZE 0x80000 # After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 4000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1788.cfg b/tcl/target/lpc1788.cfg index e986353..2f1820a 100644 --- a/tcl/target/lpc1788.cfg +++ b/tcl/target/lpc1788.cfg @@ -1,20 +1,12 @@ -# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM, +# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB SRAM set CHIPNAME lpc1788 +set CHIPSERIES lpc1700 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x10000 set CPUROMSIZE 0x80000 # After reset the chip is clocked by the ~12MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# # CCLK is the core clock frequency in KHz set CCLK 12000 -#Include the main configuration file. -source [find target/lpc17xx.cfg]; - -# if srst is not fitted, use SYSRESETREQ to perform a soft reset -cortex_m reset_config sysresetreq +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg deleted file mode 100644 index 372107f..0000000 --- a/tcl/target/lpc17xx.cfg +++ /dev/null @@ -1,99 +0,0 @@ -# Main file for NXP LPC17xx Cortex-M3 -# -# !!!!!! -# -# This file should not be included directly, rather -# by the lpc1751.cfg, lpc1752.cfg, etc. which set the -# needed variables to the appropriate values. -# -# !!!!!! - -# LPC17xx chips support both JTAG and SWD transports. -# Adapt based on what transport is active. -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." -} - -# After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# -# CCLK is the core clock frequency in KHz -if { [info exists CCLK] } { - set _CCLK $CCLK -} else { - set _CCLK 4000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." -} - -if { [info exists CPURAMSIZE] } { - set _CPURAMSIZE $CPURAMSIZE -} else { - error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." -} - -if { [info exists CPUROMSIZE] } { - set _CPUROMSIZE $CPUROMSIZE -} else { - error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." -} - -#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) -$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE - -# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code -# (including a boot loader which verifies the flash exception table's checksum). -# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ - lpc1700 $_CCLK calc_checksum - -# Run with *real slow* clock by default since the -# boot rom could have been playing with the PLL, so -# we have no idea what clock the target is running at. -adapter_khz 10 - -# delays on reset lines -adapter_nsrst_delay 200 -if {$using_jtag} { - jtag_ntrst_delay 200 -} - -$_TARGETNAME configure -event reset-init { - # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select - # "User Flash Mode" where interrupt vectors are _not_ remapped, - # and reside in flash instead). - # - # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description - # Bit Symbol Value Description Reset - # value - # 0 MAP Memory map control. 0 - # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. - # 1 User mode. The on-chip Flash memory is mapped to address 0. - # 31:1 - Reserved. The value read from a reserved bit is not defined. NA - # - # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user - - mww 0x400FC040 0x01 -} - -# if srst is not fitted use SYSRESETREQ to -# perform a soft reset -cortex_m reset_config sysresetreq diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg new file mode 100644 index 0000000..750d8b2 --- /dev/null +++ b/tcl/target/lpc1xxx.cfg @@ -0,0 +1,159 @@ +# Main file for NXP LPC1xxx series Cortex-M0/0+/3 parts +# +# !!!!!! +# +# This file should not be included directly, rather by the lpc1114.cfg, +# lpc1343.cfg, lpc1768.cfg, etc. which set the needed variables to the +# appropriate values. +# +# !!!!!! + +# LPC11xx chips support only SWD transport. +# LPC11Uxx chips support both JTAG and SWD transports. +# LPC13xx chips support both JTAG and SWD transports. +# LPC17xx chips support both JTAG and SWD transports. +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + error "_CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc1114.cfg, lpc1343.cfg, lpc1768.cfg, etc)." +} + +# After reset the chip is clocked by an internal RC oscillator. +# LPc11xx use a 4MHz one, LPC13xx/LPC17xx use a 12MHz one. +# +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +if { [info exists CCLK] } { + set _CCLK $CCLK +} else { + error "_CCLK not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc1114.cfg, lpc1343.cfg, lpc1768.cfg, etc)." +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + error "_CPUTAPID not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc1114.cfg, lpc1343.cfg, lpc1768.cfg, etc)." +} + +if { [info exists CPURAMSIZE] } { + set _CPURAMSIZE $CPURAMSIZE +} else { + error "_CPURAMSIZE not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc1114.cfg, lpc1343.cfg, lpc1768.cfg, etc)." +} + +if { [info exists CPUROMSIZE] } { + set _CPUROMSIZE $CPUROMSIZE +} else { + error "_CPUROMSIZE not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc1114.cfg, lpc1343.cfg, lpc1768.cfg, etc)." +} + +if { [info exists CHIPSERIES] } { + set _CHIPSERIES $CHIPSERIES +} else { + error "_CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc1114.cfg, lpc1343.cfg, lpc1768.cfg, etc)." +} + +# Select a special transport if it is explicitly defined (e.g. hla_swd) +if { [info exists TRANSPORT] } { + set _TRANSPORT $TRANSPORT + transport select $_TRANSPORT +} else { + set _TRANSPORT jtag +} + +if { $_TRANSPORT == "hla_swd" } { + hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID + set _TARGETTYPE hla_target + # Update swj-dp's using_jtag global (FIXME) + set using_jtag 0 +} else { + swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + set _TARGETTYPE cortex_m +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME $_TARGETTYPE -chain-position $_TARGETNAME + +# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC17xx devices have 8/16/32kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE + +# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000) +# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000) +# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000) +# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000) +# +# All three are compatible with the "lpc1700" variant of the LPC2000 flash +# driver (same cmd51 destination boundary, and all three support 256 byte +# transfers). +# +# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ + lpc1700 $_CCLK calc_checksum + +if { $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1300" } { + # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description + # Bit Symbol Value Description + # 1:0 MAP System memory remap + # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. + # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. + # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. + # 31:2 - - Reserved. + set _SYSMEMMAP_ADDRESS 0x40048000 + set _SYSMEMMAP_VALUE 0x02 +} else if { $_CHIPSERIES == "lpc1700" } { + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description + # Bit Symbol Value Description Reset + # value + # 0 MAP Memory map control. 0 + # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. + # 1 User mode. The on-chip Flash memory is mapped to address 0. + # 31:1 - Reserved. The value read from a reserved bit is not defined. NA + # + # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user + + set _SYSMEMMAP_ADDRESS 0x400FC040 + set _SYSMEMMAP_VALUE 0x01 +} + +# Run with *real slow* clock by default since the +# boot rom could have been playing with the PLL, so +# we have no idea what clock the target is running at. +adapter_khz 10 + +# delays on reset lines +adapter_nsrst_delay 200 +if {$using_jtag} { + jtag_ntrst_delay 200 +} + +$_TARGETNAME configure -event reset-init { + mww $_SYSMEMMAP_ADDRESS $_SYSMEMMAP_VALUE +} + +# LPC11xx (Cortex M0 core) supports SYSRESETREQ +# LPC13xx/LPC17xx (Cortex M3 core) supports SYSRESETREQ +# +# If we're using a low-level cortex_m target, enable SYSRESETREQ reset +# configuration. +if { $_TARGETTYPE == "cortex_m" } { + cortex_m reset_config sysresetreq +} -- ------------------------------------------------------------------------------ Managing the Performance of Cloud-Based Applications Take advantage of what the Cloud has to offer - Avoid Common Pitfalls. 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