This is an automated email from Gerrit.
Angus Gratton (g...@projectgus.com) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/1966
-- gerrit
commit 0c300b32774ea074cbf3f31c126b29d2d953780a
Author: Angus Gratton <g...@projectgus.com>
Date: Fri Feb 14 12:53:05 2014 +1100
AT91SAM4L: Allow processor to come out of reset into run or halt.
ATSAM4L has a "System Manager Access Port" (SMAP) that holds the CPU
in reset if TCK is low when SnRST (N_RESET) is deasserted.
When we write to the SMAP to let the CPU out of reset we also need to
have prepared the CPU to immediately halt if we're issuing a 'reset
halt', otherwise it goes immediately to the run state.
For details see datasheet 42023E–SAM–07/2013 especially sections
8.8.8 & 8.11.7, the latter describes how to reset into a halted CPU.
Tested w/ ft2232 JTAG (Olimex ARM-USB-TINY-H.) I don't have a
CMSIS-DAP adapter to test with (this is what the original AT91SAM4L
support used, integrated on a SAM4L eval board.)
Speculative Cautionary Note:
The SMAP won't hold the CPU in reset if the JTAG TCK line is high when
NSTRST (ie N_RESET) deasserts. I believe JTAG specs require TCK to
idle low, so in theory it should be low when N_RESET deasserts. SWD
appears to do the same, but I'm not 100% on that.
My ft2232h adapter shows the falling edge of TCK simultaneously with
N_RESET rising/deasserting so it's possible with some adapters or
cabling setups there will be a timing race, TCK will still be "high"
when N_RESET deasserts, and the ATSAM4L won't be held in reset and
will come up into the "run" state. This seems unlikely but if your
SAM4L won't reset cleanly into halt then maybe look at the timing of
N_RESET/TCK on an oscilloscope. Working around this hypothetical issue
may be as trivial as placing a small "sleep" into a reset-deassert-pre
hook so there's a gap between TCK idling and N_RESET releasing. I
didn't put the sleep in as this is 100% speculation on my part at this
point.
Why Atmel thought this feature was a good idea at all is largely
beyond me.
Change-Id: I56dd499bcb654202552aa077849548030670b10a
Signed-off-by: Angus Gratton <g...@projectgus.com>
diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index cc2941a..c648d53 100644
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -46,7 +46,7 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
halt
}
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG =
0.5MHz
+# JTAG speed should be <= F_CPU/6. On SAM4S F_CPU after reset is 4 MHz, so use
F_JTAG = 0.5MHz
#
# Since we may be running of an RC oscilator, we crank down the speed a
# bit more to be on the safe side. Perhaps superstition, but if are
diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg
index 590d78f..16fb1ef 100644
--- a/tcl/target/at91sam4lXX.cfg
+++ b/tcl/target/at91sam4lXX.cfg
@@ -2,7 +2,61 @@
#
source [find target/at91sam4XXX.cfg]
+source [find mem_helper.tcl]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME
+$_TARGETNAME configure -event reset-deassert-post at91sam4l_reset_deassert_post
+
+proc init_reset { mode } {
+ jtag arp_init-reset
+ # Before we exit reset, we need to know whether we're coming out to run or
to halt
+ #
+ # Can't access it from the reset-deassert-post, so we store it in
+ # a global variable here toread back later
+ global at91sam4l_pending_halt
+ set at91sam4l_pending_halt 0
+ if { 0 == [string compare $mode halt] } {
+ set at91sam4l_pending_halt 1
+ }
+ if { 0 == [string compare $mode init] } {
+ set at91sam4l_pending_halt 1;
+ }
+}
+
+# SAM4L SMAP will hold the CPU in reset if TCK is low when nRESET
+# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).
+#
+# We need to configure whether we want to run or halt out of reset,
+# then instruct the SMAP to let us out of reset
+proc at91sam4l_reset_deassert_post {} {
+ global at91sam4l_pending_halt
+
+ # Register addresses/masks we need
+ set ADDR_DCB_DHCSR 0xE000EDF0
+ set BIT_DHCSR_DEBUGKEY [expr 0xA05F << 16]
+ set BIT_DHCSR_DEBUGEN [expr 1 << 0]
+ set ADDR_DCB_DEMCR 0xE000EDFC
+ set BIT_DEMCR_VC_CORERESET [expr 1 << 0]
+ set ADDR_SMAP_SCR 0x400A3008
+ set BIT_HCR [expr 1 << 1]
+
+ poll on
+ sleep 20
+
+ if { $at91sam4l_pending_halt } {
+ # Set reset vector catch so we halt when reset releases
+ mww $ADDR_DCB_DEMCR [expr [ mrw $ADDR_DCB_DEMCR ] |
$BIT_DEMCR_VC_CORERESET ]
+ mww $ADDR_DCB_DHCSR [expr $BIT_DHCSR_DEBUGEN | $BIT_DHCSR_DEBUGKEY ]
+ }
+
+ # SCR.HCR, release reset
+ mww $ADDR_SMAP_SCR $BIT_HCR
+}
+
+# Without SRST (wired to N_RESET) SAM4L won't reset cleanly
+reset_config srst_only
+
+# SAM4L starts from POR with SYSCLK set to 115kHz RCLOCAL, needs slow JTAG
speed
+adapter_khz 15
--
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