This is an automated email from Gerrit. Andrey Smirnov ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2088
-- gerrit commit 97e7a5743f99d57a360e29b313bef8c8317784ee Author: Andrey Smirnov <[email protected]> Date: Thu Apr 3 14:59:44 2014 -0700 [RFC] cortex_m: Do additional initialization during reset SAM4L requires additional steps to be taken right after SYSRESETREQ is issued in order to function robustly(see comments for details). I also suspect that the code added in c90c48b00bacc8c0aa8b95b3e51c84835410e424 was for MCU that was exhibiting the same behavior and issuing additional mem_ap_read_atomic_u32 was inadvertently clearing sticky bit thus fixing the problem. This change is related to commit http://openocd.zylin.com/#/c/1995/ Change-Id: I741c95a809bfd60d930cec9482239e4796a62326 Signed-off-by: Andrey Smirnov <[email protected]> diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index dc8d344..4b83d03 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1069,18 +1069,47 @@ static int cortex_m_assert_reset(struct target *target) "handler to reset any peripherals or configure hardware srst support."); } - { - /* I do not know why this is necessary, but it - * fixes strange effects (step/resume cause NMI - * after reset) on LM3S6918 -- Michael Schwingen - */ - uint32_t tmp; - retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); - if (retval != ERROR_OK) + uint32_t ctrlstat; + int timeout = 100; + /* + SAM4L needs to execute security initalization + startup sequence before AP access would be enabled. + During the intialization CDBGPWRUPACK is pulled low and we + need to wait for it to be set to 1 again. + */ + do { + retval = dap_dp_read_atomic_u32(swjdp, DP_CTRL_STAT, &ctrlstat); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read CTRL/STAT register"); return retval; + } + } while (!(ctrlstat & CDBGPWRUPACK) && --timeout); + + if (!timeout) { + LOG_ERROR("Timed out waitnig for CDBGPWRUPACK"); + return ERROR_FAIL; + } + + /* + Some debug dongles do more than asked for(e.g. EDBG + from Atmel) behind the scene and issuing an AP write + for AIRCR may result in more than just APACC SWD + transaction, which in turn can possibly set sticky + error bit in CTRL/STAT register of the DP, so if + that happend we need to clear it by issuing AP + ABORT. + */ + uint8_t ack; + if (ctrlstat & SSTICKYERR) { + retval = dap_ap_abort_atomic(swjdp, &ack); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to queue AP ABORT"); + return retval; + } } } + target->state = TARGET_RESET; jtag_add_sleep(50000); diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg index 77ff98a..93799a2 100644 --- a/tcl/target/at91sam4lXX.cfg +++ b/tcl/target/at91sam4lXX.cfg @@ -5,7 +5,3 @@ source [find target/at91sam4XXX.cfg] set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME - -# if srst is not fitted use VECTRESET to perform a soft reset -# this will only reset the core, not the peripherals -cortex_m reset_config vectreset -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
