hi all:
I have some question about cortex_a_read_apb_ab_memory in cortex_a.c
>From spec,
"A write to the DBGITR does not trigger an instruction for execution.
Instead, the debug logic latches the
instruction written to DBGITR, and retains this value until either a
new value is written to DBGITR, or
software changes the access mode. "
But in the beginning of cortex_a_read_apb_ab_memory, we use
u8buf_ptr[2] to put ITR instructions and DSCR with DCC_FAST_MODE
that mean the 1st ITR instruction will be executed, since DCC is not
FAST_MODE at that time.
Shall we change the flow like below?
thanks for your help in advance,
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
old mode 100644
new mode 100755
index 7d58ab3..335166f
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2005,12 +2005,12 @@ static int cortex_a_read_apb_ab_memory(struct
target *target,
* in one combined write (since they are adjacent registers)
*/
u8buf_ptr = buf;
- target_buffer_set_u32(target, u8buf_ptr, ARMV4_5_LDC(0, 1, 0,
1, 14, 5, 0, 4));
dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_FAST_MODE;
- target_buffer_set_u32(target, u8buf_ptr + 4, dscr);
- /* group the 2 access CPUDBG_ITR 0x84 and CPUDBG_DSCR 0x88 */
- retval += mem_ap_sel_write_buf(swjdp, armv7a->debug_ap, u8buf_ptr, 4, 2,
- armv7a->debug_base + CPUDBG_ITR);
+ target_buffer_set_u32(target, u8buf_ptr , dscr);
+ retval +=
mem_ap_sel_write_atomic_u32(swjdp,armv7a->debug_ap,armv7a->debug_base
+ CPUDBG_DSCR,*u8buf_ptr);
+ target_buffer_set_u32(target, u8buf_ptr + 4, ARMV4_5_LDC(0, 1,
0, 1, 14, 5, 0, 4));
+ retval +=
mem_ap_sel_write_atomic_u32(swjdp,armv7a->debug_ap,armv7a->debug_base
+ CPUDBG_ITR,*u8buf_ptr);
+
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