Hello developers,
Thank you for a good and useful freeware project.
I'm working on support for Cypress PSoC 4. These chips have Cortex M0 CPU
and SWD debugging interface, so OpenOCD almost works.
PSoC 4 flash programming is managed by system ROM routines calls.
I wrote a flash driver for it. It basically works. I'll send a source to
gerrit soon
(after cleaning up).
The main problem is not working "reset halt". PSoC 4 device executes a
system
initialization code from system ROM after reset. This code subsequently
jumps
to user flash reset vector address. Unfortunately the system ROM code is
protected from reading and debugging. It complicates halting after reset
a lot.
When standard Cortex M driver sets VC_CORERESET and resets the device,
it disconnects from SWD debugging. OpenOCD with ftdi adapter needs to be
completely restarted. ST-Link v2 can reconnect but long time after user
flash
execution begins.
I know only one way how to halt the device before executing:
In a register TEST_MODE there is a flag which prevents system initialization
code from passing control to user flash.
"reset halt" would look like this:
mww 0x40030014 0x80000000 # TEST_MODE flag activate
psoc4.cpu arp_reset assert 0
psoc4.cpu arp_reset deassert 0
psoc4.cpu arp_waitstate running 200
psoc4.cpu arp_halt
psoc4.cpu arp_waitstate halted 200
mem2array value 32 0 2 # get reset vector
reg pc [expr $value(1) & 0xfffffffe ]
reg msp $value(0) # set PC and SP registers to reset values
mww 0x40030014 0 # TEST_MODE flag deactivate
I'm not able to fit this into the conception of Advanced Reset Process
events.
I need to change $halt parameter for arp_reset assert/deassert
in ocd_process_reset_inner. I also need to check what type of reset is
going on
in reset-assert-pre and reset-deassert-post events.
I know very little about jim tcl and OpenOCD internals so please help.
Tomas
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