On Sun, Sep 7, 2014 at 10:29 PM, Jens Bauer <[email protected]> wrote:
> Hi all.
>
> I just had this strange experience. It all sounds very unreal.
>
> First of all: a NOP that is HardFaulting. [...]
What I find peculiar, is that ... reading memory from OpenOCD seems to be
> inconsistent.
>
Hi!
Just a thought... I have no experience with the LPC controllers but I
assume that they, like most, need a configurable number of wait-states on
flash access, depending on clock speed, Vdd range and so on. Is it
configured correctly? Maybe try to add an extra wait-state to see if it
makes a difference. Perhaps the oddly behaving addresses belong to flash
cells that are on the limit, and temperature increase pushes it over after
a while...
If the target crashes on it's own, I think we can rule out OpenOCD, for now.
I have no idea how the disassemble routine handles odd/even addresses. I
guess the correct address to pass is the even one, without the T-bit set.
/Andreas
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