This is an automated email from Gerrit. chechun Kuo ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2299
-- gerrit commit 062650023f7db980974877d38eab12c09d4e80d0 Author: chechun Kuo <[email protected]> Date: Sun Sep 14 20:42:04 2014 +0800 src/target/cortex_a.c: put assembly instruction in IDR after DCC change to FAST mode and then dummy read DBGDRTTXext for later read working properly In original program, the data transfer instruction (ldc p14, c5, [r0],4) will be executed before the DTR mode setting to fast mode. So we write IDR and DCC_FAST_MODE separately. Meanwhile, from the spec, DDI 0406C section C8.2.2, for FAST mode, "If the issued instruction writes to DBGDTRTXint, the instruction does not affect the value returned from this read of DBGDTRTXext. That is, this instruction can write the next DBGDTRTXext value to be read.", so we add a dummy read after we change the DCC as FAST mode. Change-Id: Ie9ea267d85d4b5eadbc55fb5b68f96d35b9d9957 Signed-off-by: chechun Kuo <[email protected]> diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 7d58ab3..bfee656 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1952,8 +1952,8 @@ static int cortex_a_read_apb_ab_memory(struct target *target, int end_byte = (address + total_bytes) & 0x3; struct reg *reg; uint32_t dscr; + uint32_t tmp; uint8_t *tmp_buff = NULL; - uint8_t buf[8]; uint8_t *u8buf_ptr; LOG_DEBUG("Reading APB-AP memory address 0x%" PRIx32 " size %" PRIu32 " count%" PRIu32, @@ -2004,13 +2004,12 @@ static int cortex_a_read_apb_ab_memory(struct target *target, * and the DTR mode setting to fast mode * in one combined write (since they are adjacent registers) */ - u8buf_ptr = buf; - target_buffer_set_u32(target, u8buf_ptr, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4)); dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_FAST_MODE; - target_buffer_set_u32(target, u8buf_ptr + 4, dscr); - /* group the 2 access CPUDBG_ITR 0x84 and CPUDBG_DSCR 0x88 */ - retval += mem_ap_sel_write_buf(swjdp, armv7a->debug_ap, u8buf_ptr, 4, 2, - armv7a->debug_base + CPUDBG_ITR); + retval += mem_ap_sel_write_atomic_u32(swjdp,armv7a->debug_ap,armv7a->debug_base + CPUDBG_DSCR,dscr); + retval += mem_ap_sel_write_atomic_u32(swjdp,armv7a->debug_ap,armv7a->debug_base + CPUDBG_ITR,ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4)); + /* dummy read DTRTX for triggerring IRT command filled in */ + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, + armv7a->debug_base + CPUDBG_DTRTX, &tmp); if (retval != ERROR_OK) goto error_unset_dtr_r; -- ------------------------------------------------------------------------------ Want excitement? Manually upgrade your production database. When you want reliability, choose Perforce Perforce version control. Predictably reliable. http://pubads.g.doubleclick.net/gampad/clk?id=157508191&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
