This is an automated email from Gerrit. chechun Kuo ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2300
-- gerrit commit 901f78c473deca1a1702d3f82a85c6ebbb03ddaa Author: chechun Kuo <[email protected]> Date: Mon Sep 15 14:30:29 2014 +0800 src/target/cortex_a.c: put assembly instruction in IDR after DCC change to FAST mode and then dummy read DBGDRTTXext for later read working properly fix style problems for previous patch Change-Id: I1f6fe1f0851b981ad5017da00db900b68e39b069 Signed-off-by: chechun Kuo <[email protected]> diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index bfee656..53303b4 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2005,8 +2005,9 @@ static int cortex_a_read_apb_ab_memory(struct target *target, * in one combined write (since they are adjacent registers) */ dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_FAST_MODE; - retval += mem_ap_sel_write_atomic_u32(swjdp,armv7a->debug_ap,armv7a->debug_base + CPUDBG_DSCR,dscr); - retval += mem_ap_sel_write_atomic_u32(swjdp,armv7a->debug_ap,armv7a->debug_base + CPUDBG_ITR,ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4)); + retval += mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, dscr); + retval += mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, + armv7a->debug_base + CPUDBG_ITR, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4)); /* dummy read DTRTX for triggerring IRT command filled in */ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DTRTX, &tmp); -- ------------------------------------------------------------------------------ Want excitement? Manually upgrade your production database. When you want reliability, choose Perforce Perforce version control. Predictably reliable. http://pubads.g.doubleclick.net/gampad/clk?id=157508191&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
