This is an automated email from Gerrit. Kent Brinkley ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2305
-- gerrit commit 297e8e08a6399bf24387dbadda68a9f31a5a3dd9 Author: Kent Brinkley <[email protected]> Date: Fri Sep 19 08:30:56 2014 -0700 Added additional error checking and debug logging messages to aid in identifying failures Change-Id: I9d2009f74837d8f521ef64221cb65858c216f8fa Signed-off-by: Kent Brinkley <[email protected]> diff --git a/src/target/mips32.c b/src/target/mips32.c index d842705..2568118 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -4,7 +4,7 @@ * * * Copyright (C) 2008 by David T.L. Wong * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * [email protected] * * * * Copyright (C) 2011 by Drasko DRASKOVIC * @@ -198,11 +198,19 @@ int mips32_save_context(struct target *target) struct mips_ejtag *ejtag_info = &mips32->ejtag_info; /* read core registers */ - mips32_pracc_read_regs(ejtag_info, mips32->core_regs); - + int retval = mips32_pracc_read_regs(ejtag_info, mips32->core_regs); + if (retval != ERROR_OK) { + LOG_DEBUG("mips32_pracc_read_regs failed"); + return retval; + } for (i = 0; i < MIPS32NUMCOREREGS; i++) { - if (!mips32->core_cache->reg_list[i].valid) - mips32->read_core_reg(target, i); + if (!mips32->core_cache->reg_list[i].valid) { + retval = mips32->read_core_reg(target, i); + if (retval != ERROR_OK) { + LOG_DEBUG("mips32->read_core_reg failed"); + return retval; + } + } } return ERROR_OK; @@ -562,11 +570,11 @@ int mips32_configure_break_unit(struct target *target) } /* check if target endianness settings matches debug control register */ - if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) - && (target->endianness == TARGET_LITTLE_ENDIAN)) || - (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) - && (target->endianness == TARGET_BIG_ENDIAN))) + if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) || + (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN))) { LOG_WARNING("DCR endianness settings does not match target settings"); + LOG_WARNING("Config file does not match DCR endianness"); + } LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints); diff --git a/src/target/mips32.h b/src/target/mips32.h index 951b2ed..176cb50 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -63,6 +63,7 @@ #define MIPS32_ARCH_REL1 0x0 #define MIPS32_ARCH_REL2 0x1 +#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000 /* offsets into mips32 core register cache */ enum { MIPS32_PC = 37, diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index e97626c..1fa1ab4 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -89,22 +89,26 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) { uint32_t ejtag_ctrl; long long then = timeval_ms(); + int timeout; + int retval; /* wait for the PrAcc to become "1" */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); while (1) { ejtag_ctrl = ejtag_info->ejtag_ctrl; - int retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (retval != ERROR_OK) + retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) { + LOG_ERROR("mips_ejtag_drscan_32 Failed"); return retval; + } if (ejtag_ctrl & EJTAG_CTRL_PRACC) break; - int timeout = timeval_ms() - then; + timeout = timeval_ms() - then; if (timeout > 1000) { - LOG_DEBUG("DEBUGMODULE: No memory access in progress!"); + LOG_ERROR("Timeout: No memory access in progress!"); return ERROR_JTAG_DEVICE_ERROR; } } @@ -117,8 +121,10 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) static int mips32_pracc_read_ctrl_addr(struct mips_ejtag *ejtag_info) { int retval = wait_for_pracc_rw(ejtag_info, &ejtag_info->pa_ctrl); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("wait_for_pracc_rw failed"); return retval; + } mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); ejtag_info->pa_addr = 0; @@ -141,6 +147,7 @@ int mips32_pracc_clean_text_jump(struct mips_ejtag *ejtag_info) { uint32_t jt_code = MIPS32_J((0x0FFFFFFF & MIPS32_PRACC_TEXT) >> 2); int retval; + int log_msg = 0; /* do 3 0/nops to clean pipeline before a jump to pracc text, NOP in delay slot */ for (int i = 0; i != 5; i++) { @@ -163,16 +170,23 @@ int mips32_pracc_clean_text_jump(struct mips_ejtag *ejtag_info) if (ejtag_info->mode != 0) /* done, queued mode won't work with lexra cores */ return ERROR_OK; - retval = mips32_pracc_read_ctrl_addr(ejtag_info); - if (retval != ERROR_OK) - return retval; - - if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT) { /* LEXRA/BMIPS ?, shift out another NOP */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); - mips_ejtag_drscan_32_out(ejtag_info, MIPS32_NOP); - retval = mips32_pracc_finish(ejtag_info); + for (int i = 0; i != 2; i++) { + retval = mips32_pracc_read_ctrl_addr(ejtag_info); if (retval != ERROR_OK) return retval; + + if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT) { /* LEXRA/BMIPS ?, shift out another NOP */ + if (log_msg == 0) { + LOG_DEBUG("testing LEXRA/BMIPS ?, shift out another NOP, max 2 fix"); + log_msg = 1; + } + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); + mips_ejtag_drscan_32_out(ejtag_info, MIPS32_NOP); + retval = mips32_pracc_finish(ejtag_info); + if (retval != ERROR_OK) + return retval; + } else + break; } return ERROR_OK; @@ -194,8 +208,10 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct if (restart) { if (restart_count < 3) { /* max 3 restarts allowed */ retval = mips32_pracc_clean_text_jump(ejtag_info); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("mips32_pracc_clean_text_jump failed"); return retval; + } } else return ERROR_JTAG_DEVICE_ERROR; restart_count++; @@ -205,8 +221,10 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct } retval = mips32_pracc_read_ctrl_addr(ejtag_info); /* update current pa info: control and address */ - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("mips32_pracc_read_ctrl_addr failed"); return retval; + } /* Check for read or write access */ if (ejtag_info->pa_ctrl & EJTAG_CTRL_PRNW) { /* write/store access */ @@ -230,8 +248,10 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct uint32_t data = 0; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); retval = mips_ejtag_drscan_32(ejtag_info, &data); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("mips_ejtag_drscan_32 failed"); return retval; + } /* store data at param out, address based offset */ param_out[(ejtag_info->pa_addr - MIPS32_PRACC_PARAM_OUT) / 4] = data; @@ -308,11 +328,15 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct } /* finish processor access, let the processor eat! */ retval = mips32_pracc_finish(ejtag_info); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("mips32_pracc_finish failed"); return retval; + } - if (instr == MIPS32_DRET) /* after leaving debug mode nothing to do */ + if (instr == MIPS32_DRET) { /* after leaving debug mode nothing to do */ + LOG_DEBUG("MIPS32_DRET executed"); return ERROR_OK; + } if (store_pending == 0 && pass) { /* store access done, but after passing pracc text */ LOG_DEBUG("warning: store access pass pracc text"); @@ -1016,8 +1040,10 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are int retval, i; uint32_t val, ejtag_ctrl, address; - if (source->size < MIPS32_FASTDATA_HANDLER_SIZE) + if (source->size < MIPS32_FASTDATA_HANDLER_SIZE) { + LOG_ERROR("source->size (%x) < MIPS32_FASTDATA_HANDLER_SIZE", source->size); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } if (write_t) { handler_code[8] = MIPS32_LW(11, 0, 8); /* load data from probe at fastdata area */ @@ -1041,8 +1067,10 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) { retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("Error: wait_for_pracc_rw: ejtag_ctrl: 0x%8.8x", ejtag_ctrl); return retval; + } mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32_out(ejtag_info, jmp_code[i]); @@ -1055,18 +1083,24 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are /* wait PrAcc pending bit for FASTDATA write */ retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("wait_for_pracc_rw failed"); return retval; + } /* next fetch to dmseg should be in FASTDATA_AREA, check */ address = 0; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); retval = mips_ejtag_drscan_32(ejtag_info, &address); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("mips_ejtag_drscan_32 failed"); return retval; + } - if (address != MIPS32_PRACC_FASTDATA_AREA) + if (address != MIPS32_PRACC_FASTDATA_AREA) { + LOG_ERROR("address != MIPS32_PRACC_FASTDATA_AREA - 0x%8.8x", address); return ERROR_FAIL; + } /* Send the load start address */ val = addr; @@ -1074,8 +1108,10 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are mips_ejtag_fastdata_scan(ejtag_info, 1, &val); retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("wait_for_pracc_rw failed"); return retval; + } /* Send the load end address */ val = addr + (count - 1) * 4; @@ -1089,25 +1125,32 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are for (i = 0; i < count; i++) { jtag_add_clocks(num_clocks); retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("mips_ejtag_fastdata_scan falied"); return retval; - } + } + } + retval = jtag_execute_queue(); if (retval != ERROR_OK) { - LOG_ERROR("fastdata load failed"); + LOG_ERROR("call to \"jtag_execute_queue\" failed - fastdata load failed"); return retval; } retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("call to \"wait_for_pracc_rw\" failed - fastdata load failed with 0x%8.8" PRIx32 "", retval); return retval; + } address = 0; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); retval = mips_ejtag_drscan_32(ejtag_info, &address); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("mips_ejtag_drscan_32 failed - %x", retval); return retval; + } if (address != MIPS32_PRACC_TEXT) LOG_ERROR("mini program did not return to start"); diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 5b740cc..48d8c9f 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -60,16 +60,19 @@ static int mips_m4k_examine_debug_reason(struct target *target) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { if (ejtag_info->debug_caps & EJTAG_DCR_IB) { /* get info about inst breakpoint support */ - retval = target_read_u32(target, - ejtag_info->ejtag_ibs_addr, &break_status); - if (retval != ERROR_OK) + retval = target_read_u32(target, ejtag_info->ejtag_ibs_addr, &break_status); + if (retval != ERROR_OK) { + LOG_DEBUG("target_read_u32 failed"); return retval; + } if (break_status & 0x1f) { /* we have halted on a breakpoint */ retval = target_write_u32(target, ejtag_info->ejtag_ibs_addr, 0); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_write_u32 failed"); return retval; + } target->debug_reason = DBG_REASON_BREAKPOINT; } } @@ -78,14 +81,18 @@ static int mips_m4k_examine_debug_reason(struct target *target) /* get info about data breakpoint support */ retval = target_read_u32(target, ejtag_info->ejtag_dbs_addr, &break_status); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_read_u32 failed"); return retval; + } if (break_status & 0x1f) { /* we have halted on a breakpoint */ retval = target_write_u32(target, ejtag_info->ejtag_dbs_addr, 0); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_write_u32 failed"); return retval; + } target->debug_reason = DBG_REASON_WATCHPOINT; } } @@ -99,16 +106,30 @@ static int mips_m4k_debug_entry(struct target *target) struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - mips32_save_context(target); + int retval = mips32_save_context(target); + if (retval != ERROR_OK) { + LOG_DEBUG("mips32_save_context failed"); + return retval; + } /* make sure stepping disabled, SSt bit in CP0 debug register cleared */ - mips_ejtag_config_step(ejtag_info, 0); + retval = mips_ejtag_config_step(ejtag_info, 0); + if (retval != ERROR_OK) { + LOG_DEBUG("mips_ejtag_config_step failed"); + return retval; + } /* make sure break unit configured */ - mips32_configure_break_unit(target); + retval = mips32_configure_break_unit(target); + if (retval != ERROR_OK) { + LOG_DEBUG("mips32_configure_break_unit failed"); + return retval; + } /* attempt to find halt reason */ - mips_m4k_examine_debug_reason(target); + retval = mips_m4k_examine_debug_reason(target); + if (retval != ERROR_OK) + return retval; /* default to mips32 isa, it will be changed below if required */ mips32->isa_mode = MIPS32_ISA_MIPS32; @@ -194,8 +215,10 @@ static int mips_m4k_poll(struct target *target) /* read ejtag control reg */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG ("mips_ejtag_drscan_32 failed: ejtag_ctrl = 0x%8.8x", ejtag_ctrl); return retval; + } /* clear this bit before handling polling * as after reset registers will read zero */ @@ -206,8 +229,10 @@ static int mips_m4k_poll(struct target *target) mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG ("mips_ejtag_drscan_32 failed: ejtag_ctrl"); return retval; + } LOG_DEBUG("Reset Detected"); } @@ -226,28 +251,36 @@ static int mips_m4k_poll(struct target *target) mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); target->state = TARGET_HALTED; retval = mips_m4k_debug_entry(target); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG ("mips_m4k_debug_entry failed"); return retval; + } if (target->smp && ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))) { retval = update_halt_gdb(target); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG ("update_halt_gdb failed"); return retval; + } } target_call_event_callbacks(target, TARGET_EVENT_HALTED); } else if (target->state == TARGET_DEBUG_RUNNING) { target->state = TARGET_HALTED; retval = mips_m4k_debug_entry(target); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG ("mips_m4k_debug_entry failed"); return retval; + } if (target->smp) { retval = update_halt_gdb(target); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG ("update_halt_gdb failed"); return retval; + } } target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); @@ -384,15 +417,31 @@ static int mips_m4k_single_step_core(struct target *target) struct mips_ejtag *ejtag_info = &mips32->ejtag_info; /* configure single step mode */ - mips_ejtag_config_step(ejtag_info, 1); + int retval = mips_ejtag_config_step(ejtag_info, 1); + if (retval != ERROR_OK) { + LOG_DEBUG ("mips_ejtag_config_step failed"); + return retval; + } /* disable interrupts while stepping */ - mips32_enable_interrupts(target, 0); + retval = mips32_enable_interrupts(target, 0); + if (retval != ERROR_OK) { + LOG_DEBUG ("mips32_enable_interrupts failed"); + return retval; + } /* exit debug mode */ - mips_ejtag_exit_debug(ejtag_info); + retval = mips_ejtag_exit_debug(ejtag_info); + if (retval != ERROR_OK) { + LOG_DEBUG ("mips_ejtag_exit_debug failed"); + return retval; + } - mips_m4k_debug_entry(target); + retval = mips_m4k_debug_entry(target); + if (retval != ERROR_OK) { + LOG_DEBUG ("mips_m4k_debug_entry failed"); + return retval; + } return ERROR_OK; } @@ -569,7 +618,11 @@ static int mips_m4k_step(struct target *target, int current, register_cache_invalidate(mips32->core_cache); LOG_DEBUG("target stepped "); - mips_m4k_debug_entry(target); + int retval = mips_m4k_debug_entry(target); + if (retval != ERROR_OK) { + LOG_DEBUG ("mips_m4k_debug_entry failed"); + return retval; + } if (breakpoint) mips_m4k_set_breakpoint(target, breakpoint); @@ -640,15 +693,22 @@ static int mips_m4k_set_breakpoint(struct target *target, retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_read_memory failed"); return retval; + } retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_write_u32 failed"); return retval; + } retval = target_read_u32(target, breakpoint->address, &verify); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_read_u32 failed"); return retval; + } + if (verify != MIPS32_SDBBP) { LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); @@ -659,15 +719,22 @@ static int mips_m4k_set_breakpoint(struct target *target, retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_read_memory failed"); return retval; + } retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_write_u16 failed"); return retval; + } retval = target_read_u16(target, breakpoint->address, &verify); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_read_u16 failed"); return retval; + } + if (verify != MIPS16_SDBBP) { LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); @@ -719,8 +786,10 @@ static int mips_m4k_unset_breakpoint(struct target *target, /* check that user program has not modified breakpoint instruction */ retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t *)¤t_instr); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_read_memory failed"); return retval; + } /** * target_read_memory() gets us data in _target_ endianess. @@ -735,20 +804,32 @@ static int mips_m4k_unset_breakpoint(struct target *target, if (retval != ERROR_OK) return retval; } + else { + LOG_WARNING("memory modified: no SDBBP instruction found"); + LOG_WARNING("orignal instruction not written back to memory"); + } } else { uint16_t current_instr; /* check that user program has not modified breakpoint instruction */ retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t *)¤t_instr); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_read_memory failed"); return retval; + } current_instr = target_buffer_get_u16(target, (uint8_t *)¤t_instr); if (current_instr == MIPS16_SDBBP) { retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_DEBUG("target_write_memory failed"); return retval; + } + } + else { + LOG_WARNING("memory modified: no SDBBP instruction found"); + LOG_WARNING("orignal instruction not written back to memory"); } } } @@ -1021,6 +1102,11 @@ static int mips_m4k_write_memory(struct target *target, uint32_t address, int retval = mips_m4k_bulk_write_memory(target, address, count, buffer); if (retval == ERROR_OK) return ERROR_OK; + else + if ((retval == ERROR_TARGET_FAST_DOWNLOAD_FAILED) && + (ejtag_info->scan_delay < MIPS32_SCAN_DELAY_LEGACY_MODE)) { + return retval; + } LOG_WARNING("Falling back to non-bulk write"); } @@ -1334,7 +1420,7 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command) return ERROR_COMMAND_SYNTAX_ERROR; command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay); - if (ejtag_info->scan_delay >= 20000000) { + if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) { ejtag_info->mode = 0; command_print(CMD_CTX, "running in legacy mode"); } else { diff --git a/src/target/target.h b/src/target/target.h index 8e1c8f9..7f07b58 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -634,6 +634,7 @@ void target_handle_event(struct target *t, enum target_event e); #define ERROR_TARGET_TRANSLATION_FAULT (-309) #define ERROR_TARGET_NOT_RUNNING (-310) #define ERROR_TARGET_NOT_EXAMINED (-311) +#define ERROR_TARGET_FAST_DOWNLOAD_FAILED (-312) extern bool get_target_reset_nag(void); -- ------------------------------------------------------------------------------ Slashdot TV. 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