This is an automated email from Gerrit.

Kent Brinkley ([email protected]) just uploaded a new patch set to 
Gerrit, which you can find at http://openocd.zylin.com/2306

-- gerrit

commit dddf1e3401d61bfb6363f8aa1be369355a65a730
Author: Kent Brinkley <[email protected]>
Date:   Fri Sep 19 10:10:24 2014 -0700

    Timeout to short, correction timeout was doubled.
    
    Change-Id: I7c53cd0a3f5dfb2c36c23a29e3d3b1f778f9a5b5
    Signed-off-by: Kent Brinkley <[email protected]>

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 2568118..eeaafb9 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -4,7 +4,7 @@
  *                                                                         *
  *   Copyright (C) 2008 by David T.L. Wong                                 *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                             *
+ *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   [email protected]                                               *
  *                                                                         *
  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
@@ -209,9 +209,9 @@ int mips32_save_context(struct target *target)
                        if (retval != ERROR_OK) {
                                LOG_DEBUG("mips32->read_core_reg failed");
                                return retval;
-                       }
-               }
        }
+               }
+    }
 
        return ERROR_OK;
 }
@@ -570,8 +570,8 @@ int mips32_configure_break_unit(struct target *target)
        }
 
        /* check if target endianness settings matches debug control register */
-       if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) && (target->endianness == 
TARGET_LITTLE_ENDIAN)) ||
-               (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) && 
(target->endianness == TARGET_BIG_ENDIAN))) {
+    if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) && (target->endianness == 
TARGET_LITTLE_ENDIAN)) ||
+               (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) && 
(target->endianness == TARGET_BIG_ENDIAN))){
                LOG_WARNING("DCR endianness settings does not match target 
settings");
                LOG_WARNING("Config file does not match DCR endianness");
        }
@@ -676,7 +676,7 @@ int mips32_checksum_memory(struct target *target, uint32_t 
address,
        init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
        buf_set_u32(reg_params[1].value, 0, 32, count);
 
-       int timeout = 20000 * (1 + (count / (1024 * 1024)));
+    int timeout = (20000 * (1 + (count / (1024 * 1024))) * 2);
 
        int retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
                        crc_algorithm->address, crc_algorithm->address + 
(sizeof(mips_crc_code) - 4), timeout,

-- 

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