This is an automated email from Gerrit. Rémi PRUD'HOMME ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2313
-- gerrit commit 092b43c2b21508d132d10529f32ca4d2a00b9faf Author: Rémi PRUD'HOMME <[email protected]> Date: Tue Sep 23 09:51:38 2014 +0200 topic : add new target file for STM32L0xx New target file for STM32L0. Tested with Discovery L053 boards. Change-Id: I5c4a0353db2739c20130b718c156441eb4e9673e Signed-off-by: Rémi PRUD'HOMME <[email protected]> diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg new file mode 100755 index 0000000..78ffce4 --- /dev/null +++ b/tcl/target/stm32l0.cfg @@ -0,0 +1,94 @@ +# script for stm32l + +# +# stm32 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32l +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 10kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2800 +} + +# JTAG speed should be <= F_CPU/6. +# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz +adapter_khz 300 + +adapter_nsrst_delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0038 + # Section 24.6.2 + set _BSTAPID 0x06416041 +} + +if {[using_jtag]} { + swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc stm32l_enable_HSI {} { + # Enable HSI as clock source + echo "STM32L: Enabling HSI" + + # Set HSION in RCC_CR + mww 0x40023800 0x00000101 + + # Set HSI as SYSCLK + mww 0x40023808 0x00000001 + + # Increase JTAG speed + adapter_khz 2000 +} + +$_TARGETNAME configure -event reset-init { + stm32l_enable_HSI +} + +$_TARGETNAME configure -event reset-start { + adapter_khz 300 +} -- ------------------------------------------------------------------------------ Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
