Hi All,
I currently working on adding support for the MicroChip PIC32MZ (mips) core
used on ChipKit WiFire board provide by Digilent. I found an issue that I would
like feedback for OpenOCD group on best way to solve the problem. OpenOCD
currently supports the PIC32MX core by looking at the idcode to determine it is
PIC32Mx core (see code below). When the flag is true, the code in the
mips_m4k_assert_reset uses the flag to force a switch to ejtag controller
instead of microchip jtag controller. This check works for the MicroChip
pic32mz starter kit that I have but does not work for the Digilent WiFire board
(differ idcode).
I would like to propose a change to create a microchip target that moves away
for the idcode check and just relies on the target being MicroChip core. I
would only need to create a new assert routine and make use of the existing
code to support the mips core. The other thought was to make the script (config
file) do the switch but not sure if I could do that or not?
Any feedback would be great,
Kent
int mips_m4k_examine(struct target *target)
{
int retval;
struct mips_m4k_common *mips_m4k = target_to_m4k(target);
struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
uint32_t idcode = 0;
if (!target_was_examined(target)) {
retval = mips_ejtag_get_idcode(ejtag_info,
&idcode);
if (retval != ERROR_OK)
return retval;
ejtag_info->idcode = idcode;
if (((idcode >> 1) & 0x7FF) == 0x29) {
/* we are using a pic32mx so
select ejtag port
* as it is not selected by
default */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
LOG_DEBUG("PIC32MX Detected -
using EJTAG Interface");
mips_m4k->is_pic32mx = true;
}
}
/* init rest of ejtag interface */
retval = mips_ejtag_init(ejtag_info);
if (retval != ERROR_OK)
return retval;
retval = mips32_examine(target);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
static int mips_m4k_assert_reset(struct target *target)
{
struct mips_m4k_common *mips_m4k = target_to_m4k(target);
struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
LOG_DEBUG("target->state: %s",
target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
/* some cores support connecting while srst is asserted
* use that mode is it has been configured */
bool srst_asserted = false;
if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
(jtag_reset_config &
RESET_SRST_NO_GATING)) {
jtag_add_reset(0, 1);
srst_asserted = true;
}
/* EJTAG before v2.5/2.6 does not support EJTAGBOOT or
NORMALBOOT */
if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
if (target->reset_halt) {
/* use hardware to catch reset
*/
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
} else
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
}
if (jtag_reset_config & RESET_HAS_SRST) {
/* here we should issue a srst only, but we may
have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
jtag_add_reset(1, 1);
else if (!srst_asserted)
jtag_add_reset(0, 1);
} else {
if (mips_m4k->is_pic32mx) {
LOG_DEBUG("Using MTAP reset to
reset processor...");
/* use microchip specific MTAP
reset */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
} else {
/* use ejtag reset - not
supported by all cores */
uint32_t ejtag_ctrl =
ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset
(PRRST) to reset processor...");
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
}
}
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