I have posted a fix 2359 http://openocd.zylin.com/#/c/2359 to Gerrit for a bug I tracked down in the SPIFI flash write. I was wondering if you can take a look and review it.
I found on my board it was locking up the SPI flash chip because the last flash write command wasn't ended with CS going high and I had to power cycle the board after flashing. This is the quickest, lowest impact fix I could make by just adding one more instruction to the embedded assembly program right before it exits. I notice that there is one edge case that where it might exit due to an error, but it shouldn't hurt anything in that case so it should be fine. This was found on an LPC4370 with Spansion S25FL164K QSPI flash. I don't know whether or not the problem affects other SPI devices or other LPC processors with SPIFI. Also, I am curious about the design choice to manually toggle the SPI bus commands and CS pin via the SPI peripheral and GPIO vs. using the SPIFI peripheral registers or even the spifi_rom_api calls? If the flash is supported by the bootrom, then it is likely to have been already setup properly and running. It might be simpler and allow less mode changing, etc. Even if it is not already setup (this could be checked at runtime) it could be still be initialized like init does now. Anyway, this is just curiosity about the history; I'm quite happy that the capability was there and working in any case. :) Thanks! Anders
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