This is an automated email from Gerrit. Kent Brinkley ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2401
-- gerrit commit 8e710a8157c5badd13ef4ea89086a5ce8eb9d37e Author: Kent Brinkley <[email protected]> Date: Fri Nov 21 13:03:24 2014 -0700 Consolidating commands Consolidating non core specific commands to allow support of more than a single core. Currently only the MIPS m4k core is supported, so change is done to allow additional cores (like microAptiv) to be supported. Change-Id: I5ff5905e0417c9e7b5b567c7ab46b10453d86eb3 Signed-off-by: Kent Brinkley <[email protected]> Consolidating commands Consolidating non core specific commands to allow support of more than a single core. Currently only the MIPS m4k core is supported, so change is done to allow additional cores (like microAptiv) to be supported. Change-Id: Ia3d2f859fb072428d38ea5a6930cad8f2a263a32 Signed-off-by: Kent Brinkley <[email protected]> Consolidating commands Consolidating non core specific commands to allow support of more than a single core. Currently only the MIPS m4k core is supported, so change is done to allow additional cores (like microAptiv) to be supported. Change-Id: I5bd0a898002ff087c637d663a62ce04bb874dc8b Signed-off-by: Kent Brinkley <[email protected]> Consolidating commands Consolidating non core specific commands to allow support of more than a single core. Currently only the MIPS m4k core is supported, so change is done to allow additional cores (like microAptiv) to be supported. Change-Id: Idd80960e024c2e1c8330d8701d2381bd2340e712 Signed-off-by: Kent Brinkley <[email protected]> diff --git a/src/target/mips32.c b/src/target/mips32.c index 6c8dbcc..8da1c75 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -753,18 +753,13 @@ static int mips32_verify_pointer(struct command_context *cmd_ctx, return ERROR_OK; } -/** - * MIPS32 targets expose command interface - * to manipulate CP0 registers - */ -COMMAND_HANDLER(mips32_handle_cp0_command) +int mips32_cp0_command(struct command_invocation *cmd) { int retval; struct target *target = get_current_target(CMD_CTX); struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - retval = mips32_verify_pointer(CMD_CTX, mips32); if (retval != ERROR_OK) return retval; @@ -775,28 +770,71 @@ COMMAND_HANDLER(mips32_handle_cp0_command) } /* two or more argument, access a single register/select (write if third argument is given) */ - if (CMD_ARGC < 2) - return ERROR_COMMAND_SYNTAX_ERROR; - else { - uint32_t cp0_reg, cp0_sel; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); + if (CMD_ARGC < 2) { + uint32_t value; + + if (CMD_ARGC == 0) { + for (int i = 0; i < MIPS32NUMCP0REGS; i++) { + retval = mips32_cp0_read(ejtag_info, &value, mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel); + if (retval != ERROR_OK) { + command_print(CMD_CTX, "couldn't access reg %s", mips32_cp0_regs[i].name); + return ERROR_OK; + } + + command_print(CMD_CTX, "%*s: 0x%8.8x", 14, mips32_cp0_regs[i].name, value); + } + } else { + for (int i = 0; i < MIPS32NUMCP0REGS; i++) { + /* find register name */ + if (strcmp(mips32_cp0_regs[i].name, CMD_ARGV[0]) == 0) { + retval = mips32_cp0_read(ejtag_info, &value, mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel); + command_print(CMD_CTX, "0x%8.8x", value); + return ERROR_OK; + } + } + LOG_ERROR("BUG: register '%s' not found", CMD_ARGV[0]); + return ERROR_COMMAND_SYNTAX_ERROR; + } + } else { if (CMD_ARGC == 2) { uint32_t value; - - retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); - if (retval != ERROR_OK) { - command_print(CMD_CTX, - "couldn't access reg %" PRIi32, - cp0_reg); - return ERROR_OK; + char tmp = *CMD_ARGV[0]; + + if (isdigit(tmp) == false) { + for (int i = 0; i < MIPS32NUMCP0REGS; i++) { + /* find register name */ + if (strcmp(mips32_cp0_regs[i].name, CMD_ARGV[0]) == 0) { + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); + retval = mips32_cp0_write(ejtag_info, value, mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel); + return ERROR_OK; + } + } + + LOG_ERROR("BUG: register '%s' not found", CMD_ARGV[0]); + return ERROR_COMMAND_SYNTAX_ERROR; + } else { + uint32_t cp0_reg, cp0_sel; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); + + retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { + command_print(CMD_CTX, + "couldn't access reg %" PRIi32, + cp0_reg); + return ERROR_OK; + } + + command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, + cp0_reg, cp0_sel, value); } - command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, - cp0_reg, cp0_sel, value); - } else if (CMD_ARGC == 3) { + uint32_t cp0_reg, cp0_sel; uint32_t value; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel); if (retval != ERROR_OK) { @@ -806,13 +844,46 @@ COMMAND_HANDLER(mips32_handle_cp0_command) return ERROR_OK; } command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, - cp0_reg, cp0_sel, value); + cp0_reg, cp0_sel, value); } } return ERROR_OK; } +int mips32_scan_delay_command(struct command_invocation *cmd) +{ + struct target *target = get_current_target(CMD_CTX); + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + + int retval = mips32_verify_pointer(CMD_CTX, mips32); + if (retval != ERROR_OK) + return retval; + + if (CMD_ARGC == 1) + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay); + else if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay); + if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) { + ejtag_info->mode = 0; + command_print(CMD_CTX, "running in legacy mode"); + } else { + ejtag_info->mode = 1; + command_print(CMD_CTX, "running in fast queued mode"); + } + + return ERROR_OK; +} + +COMMAND_HANDLER(mips32_handle_cp0_command) +{ + /* Call common code */ + return mips32_cp0_command(cmd); +} + COMMAND_HANDLER(mips32_handle_scan_delay_command) { struct target *target = get_current_target(CMD_CTX); @@ -841,8 +912,8 @@ static const struct command_registration mips32_exec_command_handlers[] = { .name = "cp0", .handler = mips32_handle_cp0_command, .mode = COMMAND_EXEC, - .usage = "regnum select [value]", - .help = "display/modify cp0 register", + .help = "display/modify cp0 register(s)", + .usage = "[[reg_name|regnum select] [value]]", }, { .name = "scan_delay", diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 5b740cc..ee35023 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -1212,56 +1212,8 @@ static int mips_m4k_verify_pointer(struct command_context *cmd_ctx, COMMAND_HANDLER(mips_m4k_handle_cp0_command) { - int retval; - struct target *target = get_current_target(CMD_CTX); - struct mips_m4k_common *mips_m4k = target_to_m4k(target); - struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info; - - retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k); - if (retval != ERROR_OK) - return retval; - - if (target->state != TARGET_HALTED) { - command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; - } - - /* two or more argument, access a single register/select (write if third argument is given) */ - if (CMD_ARGC < 2) - return ERROR_COMMAND_SYNTAX_ERROR; - else { - uint32_t cp0_reg, cp0_sel; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); - - if (CMD_ARGC == 2) { - uint32_t value; - retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); - if (retval != ERROR_OK) { - command_print(CMD_CTX, - "couldn't access reg %" PRIi32, - cp0_reg); - return ERROR_OK; - } - command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, - cp0_reg, cp0_sel, value); - - } else if (CMD_ARGC == 3) { - uint32_t value; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); - retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel); - if (retval != ERROR_OK) { - command_print(CMD_CTX, - "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32, - cp0_reg, cp0_sel); - return ERROR_OK; - } - command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, - cp0_reg, cp0_sel, value); - } - } - - return ERROR_OK; + /* Call common code - maintaining backward compatibility */ + return mips32_cp0_command(cmd); } COMMAND_HANDLER(mips_m4k_handle_smp_off_command) @@ -1324,25 +1276,8 @@ COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command) COMMAND_HANDLER(mips_m4k_handle_scan_delay_command) { - struct target *target = get_current_target(CMD_CTX); - struct mips_m4k_common *mips_m4k = target_to_m4k(target); - struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info; - - if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay); - else if (CMD_ARGC > 1) - return ERROR_COMMAND_SYNTAX_ERROR; - - command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay); - if (ejtag_info->scan_delay >= 20000000) { - ejtag_info->mode = 0; - command_print(CMD_CTX, "running in legacy mode"); - } else { - ejtag_info->mode = 1; - command_print(CMD_CTX, "running in fast queued mode"); - } - - return ERROR_OK; + /* Call common code - maintaining backward compatibility */ + return mips32_scan_delay_command(cmd); } static const struct command_registration mips_m4k_exec_command_handlers[] = { @@ -1350,8 +1285,8 @@ static const struct command_registration mips_m4k_exec_command_handlers[] = { .name = "cp0", .handler = mips_m4k_handle_cp0_command, .mode = COMMAND_EXEC, - .usage = "regnum [value]", .help = "display/modify cp0 register", + .usage = "[[reg_name|regnum select] [value]]", }, { .name = "smp_off", -- ------------------------------------------------------------------------------ Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server from Actuate! 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