On Fri, Jan 02, 2015 at 02:00:50PM -0500, Mark Odell wrote:
>> I think I found the patch to fix my issue. I had two issues in fact. The
first
>> issue was the wrong -dbgbase <address>. For SAMA5D36 it should be
-dbgbase
>> 0x80010000.
>Isn't it getting properly autodetected from the DAP ROM table? Have
>you tried omitting it and looking at -d3 output?
There are two functions that are called when the dbgbase is unknown, to
read the ROM table:
dap_get_debugbase(swjdp, 1, &dbgbase, &apid);
dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15, &armv7a->debug_base,
&coreidx);
The second parameter passed in both functions is the access port index
(currently hardcoded to 1). For the SAMA5D3x chips, hard coding the ap to
0 in the calls to these functions causes the ROM table to be read correctly
without specifying the dbgbase when creating the tap, because it has only
one dap for core 0.
I don't have hardware to test other Cortex-A multi core implementations,
but I suspect that using the coreidx variable that gets set to the target
coreid might be a possible solution here. (When not specified this is set
to 0).
If there is someone willing to test this on a multi-core cortex-a chip, and
verify that it doesn't break anything, I will submit a patch.
Regards
Olivier Schonken
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