Hello, Thank you for the information about SAMA5 AP arrangement.
On Sat, Jan 03, 2015 at 04:28:42PM +0200, Olivier Schonken wrote: > The second parameter passed in both functions is the access port index > (currently hardcoded to 1). For the SAMA5D3x chips, hard coding the ap to 0 > in > the calls to these functions causes the ROM table to be read correctly without > specifying the dbgbase when creating the tap, because it has only one dap for > core 0. > > I don't have hardware to test other Cortex-A multi core implementations, but I > suspect that using the coreidx variable that gets set to the target coreid > might > be a possible solution here. (When not specified this is set to 0). I'm certain this is not matching the majority of the devices already supported by OpenOCD. All SMP cores I've seen so far had ROM table entries on the same AP. -- Be free, use free (http://www.gnu.org/philosophy/free-sw.html) software! mailto:[email protected] ------------------------------------------------------------------------------ Dive into the World of Parallel Programming! The Go Parallel Website, sponsored by Intel and developed in partnership with Slashdot Media, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials and more. Take a look and join the conversation now. http://goparallel.sourceforge.net _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
