This is an automated email from Gerrit. Ed Beroset ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2470
-- gerrit commit 2c490df4c5ff759ab4b43561c45ba849dd53ab20 Author: Ed Beroset <[email protected]> Date: Sat Jan 17 17:04:10 2015 -0500 em357: added target files for em357 and em358 This patch adds support for Silicon Labs (formerly Ember) EM357 and EM358 chips and derivatives. Although the parts support both SWJ and JTAG, only the JTAG support is tested, so verification of the SWJ part would be useful. Change-Id: Ie63aed95a2f4ef1a6b955e301a51b4de1b3a5462 Signed-off-by: Ed Beroset <[email protected]> diff --git a/tcl/target/em357.cfg b/tcl/target/em357.cfg new file mode 100644 index 0000000..3d7ee0a --- /dev/null +++ b/tcl/target/em357.cfg @@ -0,0 +1,69 @@ +# +# Target configuration for the Silicon Labs EM357 chips +# +# Processor: ARM Cortex M3 +# Date: 2015-01-17 +# Author: Ed Beroset <[email protected]> + +# +# em357 family supports JTAG and SWD transports, but +# only JTAG has been tested so far +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME em357 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3ba00477 +} + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + set _BSTAPID 0x069aa62b +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME em358 +} + +if { [info exists FLASHSIZE] } { + set _FLASHSIZE $FLASHSIZE +} else { + set _FLASHSIZE 0x30000 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +swj_newdap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME em357 0x08000000 $_FLASHSIZE 0 0 $_TARGETNAME + +cortex_m reset_config sysresetreq diff --git a/tcl/target/em358.cfg b/tcl/target/em358.cfg new file mode 100644 index 0000000..a6a547f --- /dev/null +++ b/tcl/target/em358.cfg @@ -0,0 +1,21 @@ +# +# Target configuration for the Silicon Labs EM358 chips +# +# Processor: ARM Cortex M3 +# Date: 2015-01-17 +# Author: Ed Beroset <[email protected]> + +# +# em357 family supports JTAG and SWD transports, but +# only JTAG has been tested so far +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME em358 +} + +# 512K of flash in the em358 chips +set FLASHSIZE 0x80000 +source [find target/em357.cfg] -- ------------------------------------------------------------------------------ New Year. New Location. New Benefits. New Data Center in Ashburn, VA. GigeNET is offering a free month of service with a new server in Ashburn. Choose from 2 high performing configs, both with 100TB of bandwidth. Higher redundancy.Lower latency.Increased capacity.Completely compliant. http://p.sf.net/sfu/gigenet _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
