This is an automated email from Gerrit. Andreas Fritiofson ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2474
-- gerrit commit 53226a23b40f8d7c459482d4a6877a8befd3242a Author: Andreas Fritiofson <[email protected]> Date: Sun Jan 18 13:27:23 2015 +0100 Change the register value type from void* to uint8_t*. Increasing type safety to avoid byte order bugs. Also fix the byte order bugs in the cortex_m and nds32 targets uncovered by this change. Change-Id: Ic9f62963322e938a93b757f04ffc2f25d709aff2 Signed-off-by: Andreas Fritiofson <[email protected]> diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index a5230b7..3a4cd96 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1646,14 +1646,20 @@ static int cortex_m_init_target(struct command_context *cmd_ctx, struct dwt_reg_state { struct target *target; uint32_t addr; - uint32_t value; /* scratch/cache */ + uint8_t value[4]; /* scratch/cache */ }; static int cortex_m_dwt_get_reg(struct reg *reg) { struct dwt_reg_state *state = reg->arch_info; - return target_read_u32(state->target, state->addr, &state->value); + uint32_t tmp; + int retval = target_read_u32(state->target, state->addr, &tmp); + if (retval != ERROR_OK) + return retval; + + buf_set_u32(state->value, 0, 32, tmp); + return ERROR_OK; } static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf) @@ -1708,7 +1714,7 @@ static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg r->name = d->name; r->size = d->size; - r->value = &state->value; + r->value = state->value; r->arch_info = state; r->type = &dwt_reg_type; } diff --git a/src/target/etm.c b/src/target/etm.c index 5239190..75cdecd 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -281,7 +281,7 @@ static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info, reg->name = r->name; reg->size = r->size; - reg->value = &ereg->value; + reg->value = ereg->value; reg->arch_info = ereg; reg->type = &etm_scan6_type; reg++; diff --git a/src/target/nds32.c b/src/target/nds32.c index 8ab2859..6cae2c1 100644 --- a/src/target/nds32.c +++ b/src/target/nds32.c @@ -86,32 +86,32 @@ static int nds32_get_core_reg(struct reg *reg) } if (reg->valid) { + uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32); LOG_DEBUG("reading register(cached) %" PRIi32 "(%s), value: 0x%8.8" PRIx32, - reg_arch_info->num, reg->name, reg_arch_info->value); + reg_arch_info->num, reg->name, val); return ERROR_OK; } int mapped_regnum = nds32->register_map(nds32, reg_arch_info->num); if (reg_arch_info->enable == false) { - reg_arch_info->value = NDS32_REGISTER_DISABLE; + buf_set_u32(reg_arch_info->value, 0, 32, NDS32_REGISTER_DISABLE); retval = ERROR_FAIL; } else { - if ((nds32->fpu_enable == false) && - (NDS32_REG_TYPE_FPU == nds32_reg_type(mapped_regnum))) { - reg_arch_info->value = 0; + uint32_t val = 0; + if ((nds32->fpu_enable == false) + && (NDS32_REG_TYPE_FPU == nds32_reg_type(mapped_regnum))) { retval = ERROR_OK; - } else if ((nds32->audio_enable == false) && - (NDS32_REG_TYPE_AUMR == nds32_reg_type(mapped_regnum))) { - reg_arch_info->value = 0; + } else if ((nds32->audio_enable == false) + && (NDS32_REG_TYPE_AUMR == nds32_reg_type(mapped_regnum))) { retval = ERROR_OK; } else { - retval = aice_read_register(aice, - mapped_regnum, &(reg_arch_info->value)); + retval = aice_read_register(aice, mapped_regnum, &val); } + buf_set_u32(reg_arch_info->value, 0, 32, val); LOG_DEBUG("reading register %" PRIi32 "(%s), value: 0x%8.8" PRIx32, - reg_arch_info->num, reg->name, reg_arch_info->value); + reg_arch_info->num, reg->name, val); } if (retval == ERROR_OK) { @@ -139,17 +139,17 @@ static int nds32_get_core_reg_64(struct reg *reg) return ERROR_OK; if (reg_arch_info->enable == false) { - reg_arch_info->value_64 = NDS32_REGISTER_DISABLE; + buf_set_u64(reg_arch_info->value_64, 0, 64, NDS32_REGISTER_DISABLE); retval = ERROR_FAIL; } else { - if ((nds32->fpu_enable == false) && - ((FD0 <= reg_arch_info->num) && (reg_arch_info->num <= FD31))) { - reg_arch_info->value_64 = 0; + uint64_t val = 0; + if ((nds32->fpu_enable == false) + && ((FD0 <= reg_arch_info->num) && (reg_arch_info->num <= FD31))) { retval = ERROR_OK; } else { - retval = aice_read_reg_64(aice, reg_arch_info->num, - &(reg_arch_info->value_64)); + retval = aice_read_reg_64(aice, reg_arch_info->num, &val); } + buf_set_u64(reg_arch_info->value_64, 0, 64, val); } if (retval == ERROR_OK) { @@ -322,11 +322,13 @@ static int nds32_set_core_reg(struct reg *reg, uint8_t *buf) buf_set_u32(reg->value, 0, 32, 0); } else { buf_set_u32(reg->value, 0, 32, value); - aice_write_register(aice, mapped_regnum, reg_arch_info->value); + uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32); + aice_write_register(aice, mapped_regnum, val); /* After set value to registers, read the value from target * to avoid W1C inconsistency. */ - aice_read_register(aice, mapped_regnum, &(reg_arch_info->value)); + aice_read_register(aice, mapped_regnum, &val); + buf_set_u32(reg_arch_info->value, 0, 32, val); } reg->valid = true; @@ -426,14 +428,14 @@ static struct reg_cache *nds32_build_reg_cache(struct target *target, reg_list[i].reg_data_type = calloc(sizeof(struct reg_data_type), 1); if (FD0 <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) { - reg_list[i].value = &(reg_arch_info[i].value_64); + reg_list[i].value = reg_arch_info[i].value_64; reg_list[i].type = &nds32_reg_access_type_64; reg_list[i].reg_data_type->type = REG_TYPE_IEEE_DOUBLE; reg_list[i].reg_data_type->id = "ieee_double"; reg_list[i].group = "float"; } else { - reg_list[i].value = &(reg_arch_info[i].value); + reg_list[i].value = reg_arch_info[i].value; reg_list[i].type = &nds32_reg_access_type; reg_list[i].group = "general"; @@ -1549,10 +1551,14 @@ int nds32_restore_context(struct target *target) i, buf_get_u32(reg->value, 0, 32)); reg_arch_info = reg->arch_info; - if (FD0 <= reg_arch_info->num && reg_arch_info->num <= FD31) - aice_write_reg_64(aice, reg_arch_info->num, reg_arch_info->value_64); - else - aice_write_register(aice, reg_arch_info->num, reg_arch_info->value); + if (FD0 <= reg_arch_info->num && reg_arch_info->num <= FD31) { + uint64_t val = buf_get_u64(reg_arch_info->value_64, 0, 64); + aice_write_reg_64(aice, reg_arch_info->num, val); + } else { + uint32_t val = buf_get_u32(reg_arch_info->value, 0, 32); + aice_write_register(aice, reg_arch_info->num, val); + } + reg->valid = true; reg->dirty = false; } diff --git a/src/target/nds32.h b/src/target/nds32.h index eddfe7a..caca11b 100644 --- a/src/target/nds32.h +++ b/src/target/nds32.h @@ -362,8 +362,8 @@ struct nds32 { struct nds32_reg { int32_t num; - uint32_t value; - uint64_t value_64; + uint8_t value[4]; + uint8_t value_64[8]; struct target *target; struct nds32 *nds32; bool enable; diff --git a/src/target/register.h b/src/target/register.h index 354a179..66a860a 100644 --- a/src/target/register.h +++ b/src/target/register.h @@ -120,7 +120,7 @@ struct reg { uint32_t number; struct reg_feature *feature; bool caller_save; - void *value; + uint8_t *value; bool dirty; bool valid; bool exist; -- ------------------------------------------------------------------------------ New Year. New Location. New Benefits. New Data Center in Ashburn, VA. GigeNET is offering a free month of service with a new server in Ashburn. Choose from 2 high performing configs, both with 100TB of bandwidth. Higher redundancy.Lower latency.Increased capacity.Completely compliant. http://p.sf.net/sfu/gigenet _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
