Hi all, First good news: I used Angus Gratton's change #1966 and after some fiddling reset run and reset halt works properly for both sysresetreq and srst (originally worked with srst only).
It is a shame that change #1966 laying in Gerrit unmerged more than year. Without #1966 only vectreset can be used with SAM4L, adapter_khz is too high and asserting n-RESET line (even pressing reset button) locks MCU so that only power cycle restores working state because SMAP (System Manager Access Port) keeps reset active until a HCR is set in SMAP_SCR register. Now I have experience with two strange implementations of Cortex-M: PSoC4 and SAM4L. Do we have other candidates to "strange" category? "Strangers" impose two common requirements to OpenOCD code: 1) introduce a jim-tcl function to explicitly send init sequence (JTAG-to-SWD or similar) and do ahbap_debugport_init() On 13.3.2015 8:28, Paul Fertser wrote > 4. Is this the example of a target that would benefit from > ahbap_debugport_init on hardware reset deassertion? >> On Thu, Mar 12, 2015 at 10:58:59AM +0100, Tomas Vanek wrote: >> >> Probably yes. On the other hand I doubt about using it for every target. >> Why not to do reinit just when srst_pulls_trst flag is set (or introduce a >> new flag)? > I was proposing exactly that, do that debugport_init after deassertion > only if srst is available and srst pulls trst (this flag sounds > appropriate enough). I think that tcl function is much more flexible and system of arp_... functions is somewhat incomplette without it. I'd like concept of arp_waitstate - if timeout given, initialization will loop until dp access is gained or timeout expires. PSoC4 application note requires retrying init until secure initialization routines are finished and DP unlocked. Although now we need only both init seq and ahbap_debugport_init for PSoC4 and SAM4L, I propose an option to enable/disable sending JTAG-to-SWD or other target appropriate sequence. 2) add a quirk option to cortex-m to escape from cortex_m_assert_reset() just after AIRCR_SYSRESETREQ or AIRCR_VECTRESET is set cotex_m.c:1060 is problematic for both PSoC4 and SAM4L. ahbap_debugport_init() immediately follows a reset. Both "strangers" need send an init sequence (or keep trying init seq and dp init for same time in case of PSoC4) Remember your recent success with SRST timings in SWD mode. There is no need to wait due to capacitor on srst line or so. But generally I can imagine that there could be reason not to start ahbap_debugport_init() immediately but after some delay. E.g. wait for MCU to setup right clock freq or so. 3) an optional part just for nicer code at91sam4lXX.cfg in Angus Gratton's version uses cortex_m vector_catch reset cortex_m maskisr off to prepare reset vector catch. Introducing a new cortex_m function prepare_vc_reset would be better than abusing setting functions. I can do 2 and 3. Tom ------------------------------------------------------------------------------ Dive into the World of Parallel Programming The Go Parallel Website, sponsored by Intel and developed in partnership with Slashdot Media, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials and more. Take a look and join the conversation now. http://goparallel.sourceforge.net/ _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
