This is an automated email from Gerrit. Uwe Bonnes ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2707
-- gerrit commit dea94751cfb31e958c8c9088762303ca63576782 Author: Uwe Bonnes <[email protected]> Date: Thu Apr 9 18:01:35 2015 +0200 tcl: Add default hooks for STM32F0x Keep clocks running in low power modes. Stop watchdogs from interfering with the debug session. Set up PLL and increase clock at reset init. Change-Id: I232d769d893d54e4ea9411c46c56b19587b69919 Signed-off-by: Uwe Bonnes <[email protected]> diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg index ff6d7f1..1ea947a 100644 --- a/tcl/target/stm32f0x.cfg +++ b/tcl/target/stm32f0x.cfg @@ -4,6 +4,7 @@ # stm32 devices support SWD transports only. # source [find target/swj-dp.tcl] +source [find mem_helper.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -53,3 +54,33 @@ if {![using_hla]} { # perform a soft reset cortex_m reset_config sysresetreq } + +proc stm32f0x_default_reset_start {} { + # Reset clock is HSI (8 MHz) + adapter_khz 1000 +} + +proc stm32f0x_default_examine_end {} { + # Enable debug during low power modes (uses more power) + mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP + + # Stop watchdog counters during halt + mww 0x40015808 0x00001800 ;# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP +} + +proc stm32f0x_default_reset_init {} { + # Configure PLL to boost clock to HSI x 6 (48 MHz) + mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2] + mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON + mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0] + sleep 10 ;# Wait for PLL to lock + mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] + + # Boost JTAG frequency + adapter_khz 8000 +} + +# Default hooks +$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end } +$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start } +$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init } -- ------------------------------------------------------------------------------ BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT Develop your own process in accordance with the BPMN 2 standard Learn Process modeling best practices with Bonita BPM through live exercises http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual- event?utm_ source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
