This is an automated email from Gerrit. Andreas Färber ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2728
-- gerrit commit 6f39a9a308f139c91f0ebe896b01f105a684b406 Author: Andreas Färber <[email protected]> Date: Thu Apr 23 12:30:39 2015 +0200 tcl/interface: Add Digilent JTAG-HS3 config Based on tcl/interface/digilent_jtag_hs1.cfg. JTAG-HS3 has an open drain buffer on pin 14 for SRST to work with PS_SRST_B on Xilinx Zynq SoC. Change-Id: I1e9e72d0511528a61207e318aff937ae9fad5bf9 Signed-off-by: Andreas Färber <[email protected]> diff --git a/tcl/interface/ftdi/digilent_jtag_hs3.cfg b/tcl/interface/ftdi/digilent_jtag_hs3.cfg new file mode 100644 index 0000000..bb54162 --- /dev/null +++ b/tcl/interface/ftdi/digilent_jtag_hs3.cfg @@ -0,0 +1,11 @@ +# +# Digilent JTAG-HS3 +# + +interface ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0088 0x008b +# TODO ftdi_layout_signal nSRST -data 0xXXXX + +reset_config srst_push_pull -- ------------------------------------------------------------------------------ BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT Develop your own process in accordance with the BPMN 2 standard Learn Process modeling best practices with Bonita BPM through live exercises http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual- event?utm_ source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
