This is an automated email from Gerrit. David Ung ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2747
-- gerrit commit af683ccd96dd575aa41f1d8051dce154186f411b Author: David Ung <[email protected]> Date: Mon Apr 20 13:14:43 2015 -0700 aarch64: Correct target state for hardware step When using hardware step for doing stepping, the existing DSCR records the event as external debug request. This will generate a SIGINT event to GDB and causes it to stop the stepping process. For aarch64, read DESR to check if the event is a hardware step and set state to DBG_REASON_SINGLESTEP. With this patch, I can use GDB to do source level stepping in the kernel. Change-Id: I1d06f819578c74b3ac17376c67f882adddea1f52 Signed-off-by: David Ung <[email protected]> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 32d631c..7792f9b 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1073,6 +1073,7 @@ static int aarch64_debug_entry(struct target *target) struct aarch64_common *aarch64 = target_to_aarch64(target); struct armv8_common *armv8 = target_to_armv8(target); struct adiv5_dap *swjdp = armv8->arm.dap; + uint32_t tmp; LOG_DEBUG("dscr = 0x%08" PRIx32, aarch64->cpudbg_dscr); @@ -1096,6 +1097,10 @@ static int aarch64_debug_entry(struct target *target) /* Examine debug reason */ arm_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr); + mem_ap_sel_read_atomic_u32(swjdp, armv8->debug_ap, + armv8->debug_base + CPUDBG_DESR, &tmp); + if ((tmp & 0x7) == 0x4) + target->debug_reason = DBG_REASON_SINGLESTEP; /* save address of instruction that triggered the watchpoint? */ if (target->debug_reason == DBG_REASON_WATCHPOINT) { @@ -1175,12 +1180,16 @@ static int aarch64_step(struct target *target, int current, target_ulong address if (retval != ERROR_OK) return retval; + target->debug_reason = DBG_REASON_SINGLESTEP; retval = aarch64_resume(target, 1, address, 0, 0); if (retval != ERROR_OK) return retval; long long then = timeval_ms(); while (target->state != TARGET_HALTED) { + mem_ap_sel_read_atomic_u32(swjdp, armv8->debug_ap, + armv8->debug_base + CPUDBG_DESR, &tmp); + LOG_DEBUG("DESR = %#x", tmp); retval = aarch64_poll(target); if (retval != ERROR_OK) return retval; @@ -1190,13 +1199,13 @@ static int aarch64_step(struct target *target, int current, target_ulong address } } - target->debug_reason = DBG_REASON_BREAKPOINT; retval = mem_ap_sel_write_atomic_u32(swjdp, armv8->debug_ap, armv8->debug_base + CPUDBG_DECR, (tmp&(~0x4))); if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if (target->state == TARGET_HALTED) LOG_DEBUG("target stepped"); return ERROR_OK; diff --git a/src/target/armv8.h b/src/target/armv8.h index 365d687..536fc6c 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -163,6 +163,7 @@ target_to_armv8(struct target *target) /* register offsets from armv8.debug_base */ #define CPUDBG_WFAR 0x018 +#define CPUDBG_DESR 0x020 #define CPUDBG_DECR 0x024 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */ #define CPUDBG_DSCR 0x088 -- ------------------------------------------------------------------------------ One dashboard for servers and applications across Physical-Virtual-Cloud Widest out-of-the-box monitoring support with 50+ applications Performance metrics, stats and reports that give you Actionable Insights Deep dive visibility with transaction tracing using APM Insight. http://ad.doubleclick.net/ddm/clk/290420510;117567292;y _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
