This is an automated email from Gerrit. Tomas Vanek ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2778
-- gerrit commit 6aeaf334fea945c27ac18ebac95b4833f2009808 Author: Tomas Vanek <[email protected]> Date: Fri May 15 11:14:11 2015 +0200 ATSAMD, SAML, SAMR: handle reset run/halt in DSU Atmel introduced a "Device Service Unit" (DSU) that holds the CPU in reset if TCK is low when srst (RESET_N) is deasserted. Function is similar to SMAP in ATSAM4L, see http://openocd.zylin.com/2604 Without this change any use of sysresetreq or srst locks the chip in reset state until power is cycled. A new function dsu_reset_deassert is called as reset-deassert-post event handler. It optionally prepares reset vector catch and DSU reset is released then. Additionally SWD clock comment is fixed in at91samdXX.cfg and clock is lowered a bit to ensure a margin for RC oscillator frequency deviation. adapter_nsrst_delay 100 is commented out because is no more necessary after http://openocd.zylin.com/2601 Change-Id: I42e99b1b245f766616c0a0d939f60612c29bd16c Signed-off-by: Tomas Vanek <[email protected]> diff --git a/doc/openocd.texi b/doc/openocd.texi index 511bc6c..b039614 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5054,6 +5054,20 @@ the appropriate at91sam7 target. @end deffn @end deffn +@deffn {Flash Driver} at91samd +@cindex at91samd +All members of the ATSAMD, ATSAML, ATSAMR microcontroller families from +Atmel include internal flash and use ARM's Cortex-M0+ core. +This driver uses the same cmd names/syntax as @xref{at91sam3}. + +The at91samd driver adds some additional commands: +@deffn Command {at91samd dsu_reset_deassert} +This command releases internal reset held by DSU +and prepares reset vector catch in case of reset halt. +Command is used internally in event event reset-deassert-post. +@end deffn +@end deffn + @deffn {Flash Driver} avr The AVR 8-bit microcontrollers from Atmel integrate flash memory. @emph{The current implementation is incomplete.} diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c index ddca137..aec1108 100644 --- a/src/flash/nor/at91samd.c +++ b/src/flash/nor/at91samd.c @@ -25,6 +25,8 @@ #include "imp.h" #include "helper/binarybuffer.h" +#include <target/cortex_m.h> + #define SAMD_NUM_SECTORS 16 #define SAMD_PAGE_SIZE_MAX 1024 @@ -34,6 +36,7 @@ #define SAMD_DSU 0x41002000 /* Device Service Unit */ #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */ +#define SAMD_DSU_STATUSA 1 /* DSU status register */ #define SAMD_DSU_DID 0x18 /* Device ID register */ #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */ @@ -1001,8 +1004,47 @@ COMMAND_HANDLER(samd_handle_bootloader_command) return res; } + + +COMMAND_HANDLER(samd_handle_reset_deassert) +{ + struct target *target = get_current_target(CMD_CTX); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = armv7m->arm.dap; + int retval = ERROR_OK; + enum reset_types jtag_reset_config = jtag_get_reset_config(); + + /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset() + * so we just release reset held by DSU + * + * n_RESET (srst) clears the DP, so reenable debug and set vector catch here + * + * After vectreset DSU release is not needed however makes no harm + */ + if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) { + retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN); + if (retval == ERROR_OK) + retval = mem_ap_write_u32(swjdp, DCB_DEMCR, + TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + /* do not return on error here, releasing DSU reset is more important */ + } + + /* clear CPU Reset Phase Extension bit */ + int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1)); + if (retval2 != ERROR_OK) + return retval2; + + return retval; +} + static const struct command_registration at91samd_exec_command_handlers[] = { { + .name = "dsu_reset_deassert", + .handler = samd_handle_reset_deassert, + .mode = COMMAND_EXEC, + .help = "deasert internal reset held by DSU" + }, + { .name = "info", .handler = samd_handle_info_command, .mode = COMMAND_EXEC, diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg index fb3be04..c64ae27 100644 --- a/tcl/target/at91samdXX.cfg +++ b/tcl/target/at91samdXX.cfg @@ -40,15 +40,26 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAM $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz +# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N +# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2) # -# Since we may be running of an RC oscilator, we crank down the speed a -# bit more to be on the safe side. Perhaps superstition, but if are -# running off a crystal, we can run closer to the limit. Note -# that there can be a pretty wide band where things are more or less stable. +# dsu_reset_deassert configures whether we want to run or halt out of reset, +# then instruct the DSU to let us out of reset. +$_TARGETNAME configure -event reset-deassert-post { + at91samd dsu_reset_deassert +} + +# SRST (wired to RESET_N) resets debug circuitry +# srst_pulls_trst is not configured here to avoid an error raised in reset halt +reset_config srst_gates_jtag + +# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset. +# Datasheet does not specify SYSCLK to SWD clock ratio. +# Usually used SYSCLK/6 is slow, testing shows that debugging can work @ SYSCLK/2 +# but your mileage may vary. -adapter_khz 500 -adapter_nsrst_delay 100 +adapter_khz 400 +#adapter_nsrst_delay 100 if {![using_hla]} { # if srst is not fitted use SYSRESETREQ to -- ------------------------------------------------------------------------------ One dashboard for servers and applications across Physical-Virtual-Cloud Widest out-of-the-box monitoring support with 50+ applications Performance metrics, stats and reports that give you Actionable Insights Deep dive visibility with transaction tracing using APM Insight. http://ad.doubleclick.net/ddm/clk/290420510;117567292;y _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
