This is an automated email from Gerrit. Rémi PRUD'HOMME ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2784
-- gerrit commit b2f0ccb2cf8e67576912624df426b724e9a861bb Author: Rémi PRUD’HOMME <[email protected]> Date: Thu May 28 11:27:18 2015 +0200 remove trailling spaces Change-Id: Ibd7c00494fb93409811b2b71b66f1737891bce1d Signed-off-by: Rémi PRUD'HOMME <[email protected]> diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 54df0d9..9d533c5 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1879,8 +1879,8 @@ static void cortex_m_dwt_free(struct target *target) http://infocenter.arm.com/help/topic/com.arm.doc.ddi0489c/DDI0489C_cortex_m7_trm.pdf chapiter 8.3, FPU programmers model */ -/* - The cortex m7 come with three option : without FPH, Simple Precision FPU, +/* + The cortex m7 come with three option : without FPH, Simple Precision FPU, Double Precision. The value for simple precision is the same than cortex m4 The FPU version for cortex m7 are FPUv5_SP, FPUv5_DP. */ @@ -1954,9 +1954,9 @@ int cortex_m_examine(struct target *target) armv7m->arm.is_armv6m = true; } - if ((armv7m->fp_feature != FPv4_SP && - armv7m->fp_feature != FPv5_SP && - armv7m->fp_feature != FPv5_DP)&& + if ((armv7m->fp_feature != FPv4_SP && + armv7m->fp_feature != FPv5_SP && + armv7m->fp_feature != FPv5_DP) && armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) { /* free unavailable FPU registers */ size_t idx; @@ -1974,9 +1974,9 @@ int cortex_m_examine(struct target *target) if (i == 7) cortex_m->cortex_m7 = 1; - else + else cortex_m->cortex_m7 = 0; - + /* Configure trace modules */ retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr); if (retval != ERROR_OK) -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
