This is an automated email from Gerrit. Robert Jordens ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2847
-- gerrit commit fcef65b6d20b74aa46d1c81818377ce57165fc3d Author: Robert Jordens <[email protected]> Date: Thu Jul 2 00:58:38 2015 -0600 tcl: add jtagspi, xilinx-spartan6, pipistrello cfg This adds the full stack of JTAG interface (on-board FT2232C), FPGA tap (XC6S45), and jtagspi flash configuration files for the pipistrello board. http://pipistrello.saanlima.com A commandline to program the spi flash would be for example: openocd -f board/pipistrello.cfg -c "init; jtag2spi_init 0 bscan_spi_XX.bit; jtag2spi_program my_bitstream.bin 0; fpga_program; exit" Change-Id: I34092e95561914d9199104e0203a8e20ead9f360 Signed-off-by: Robert Jordens <[email protected]> diff --git a/tcl/board/pipistrello.cfg b/tcl/board/pipistrello.cfg new file mode 100644 index 0000000..b7d1416 --- /dev/null +++ b/tcl/board/pipistrello.cfg @@ -0,0 +1,5 @@ +source [find interface/ftdi/pipistrello.cfg] +set _XC6SLX45_TAPID 0x44008093 +set FPGATAPID $_XC6SLX45_TAPID +source [find cpld/xilinx-spartan6.cfg] +source [find cpld/jtagspi.cfg] diff --git a/tcl/cpld/jtagspi.cfg b/tcl/cpld/jtagspi.cfg new file mode 100644 index 0000000..9d1eca9 --- /dev/null +++ b/tcl/cpld/jtagspi.cfg @@ -0,0 +1,36 @@ +set _USER1 0x02 + +if { [info exists JTAG2SPI_IR] } { + set _JTAG2SPI_IR $JTAG2SPI_IR +} else { + set _JTAG2SPI_IR $_USER1 +} + +if { [info exists JTAG2SPI_LATENCY] } { + set _JTAG2SPI_LATENCY $JTAG2SPI_LATENCY +} else { + set _JTAG2SPI_LATENCY 1 +} + +set _PROXYNAME $_CHIPNAME.proxy +set _FLASHNAME $_CHIPNAME.spi + +target create $_PROXYNAME testee -chain-position $_FPGANAME +flash bank $_FLASHNAME jtagspi 0 0 0 0 $_PROXYNAME $_JTAG2SPI_IR $_JTAG2SPI_LATENCY + +proc jtag2spi_init {chain_id proxy_bit} { + global _PROXYNAME _FLASHNAME + pld load $chain_id $proxy_bit + reset halt + $_PROXYNAME arp_examine + flash probe $_FLASHNAME +} + +proc jtag2spi_program {bin addr} { + global _FLASHNAME + #flash erase_sector $_FLASHNAME 0 1 + #flash erase_address pad $addr $length + #flash write_bank $_FLASHNAME $bin $addr + flash write_image erase $bin $addr + flash verify_bank $_FLASHNAME $bin $addr +} diff --git a/tcl/cpld/xilinx-spartan6.cfg b/tcl/cpld/xilinx-spartan6.cfg new file mode 100644 index 0000000..0190eaa --- /dev/null +++ b/tcl/cpld/xilinx-spartan6.cfg @@ -0,0 +1,37 @@ +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc6s +} + +set _CFG_IN 0x05 +set _JSHUTDOWN 0x0d +set _JPROGRAM 0x0b +set _JSTART 0x0c +set _BYPASS 0x3f + +set _FPGANAME $_CHIPNAME.fpga +jtag newtap $_CHIPNAME fpga -irlen 6 -expected-id $FPGATAPID +pld device virtex2 $_FPGANAME + +proc fpga_program {} { + global _JSHUTDOWN _JPROGRAM _JSTART _BYPASS _FPGANAME + irscan $_FPGANAME $_JSHUTDOWN + irscan $_FPGANAME $_JPROGRAM + irscan $_FPGANAME $_JSTART + irscan $_FPGANAME $_BYPASS +} + +#xtp038 and xc3sprog approach +proc fpga_program_iprog {} { + global _JSHUTDOWN _JSTART _BYPASS _CFG_IN _FPGANAME + irscan $_FPGANAME $_JSHUTDOWN + runtest 16 + irscan $_FPGANAME $_CFG_IN + # xtp038 IPROG 16bit flipped + drscan $_FPGANAME 16 0xffff 16 0x9955 16 0x66aa 16 0x850c 16 0x7000 16 0x0004 + irscan $_FPGANAME $_JSTART + runtest 32 + irscan $_FPGANAME $_BYPASS + runtest 1 +} -- ------------------------------------------------------------------------------ Don't Limit Your Business. Reach for the Cloud. GigeNET's Cloud Solutions provide you with the tools and support that you need to offload your IT needs and focus on growing your business. Configured For All Businesses. Start Your Cloud Today. https://www.gigenetcloud.com/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
