This is an automated email from Gerrit. Matthias Welwarsky ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3028
-- gerrit commit b968e7360e4a87318f9df919ef284db3cae9cc00 Author: Matthias Welwarsky <[email protected]> Date: Fri Oct 16 10:46:35 2015 +0200 armv7a: fix debug messages regarding cache on/off state Cache bits are not level specific, remove "l1" from debug message. Also, fix data/instruction mixup in armv7a_l1_i_cache_sanity_check() Change-Id: I259665ffe62c7ada5b4f98d3fd907e93662d4091 Signed-off-by: Matthias Welwarsky <[email protected]> diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c index 172cac0..5207ee4 100644 --- a/src/target/armv7a_cache.c +++ b/src/target/armv7a_cache.c @@ -35,7 +35,7 @@ static int armv7a_l1_d_cache_sanity_check(struct target *target) /* check that cache data is on at target halt */ if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) { - LOG_DEBUG("l1 data cache is not enabled"); + LOG_DEBUG("data cache is not enabled"); return ERROR_TARGET_INVALID; } @@ -53,7 +53,7 @@ static int armv7a_l1_i_cache_sanity_check(struct target *target) /* check that cache data is on at target halt */ if (!armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) { - LOG_DEBUG("l1 data cache is not enabled"); + LOG_DEBUG("instruction cache is not enabled"); return ERROR_TARGET_INVALID; } -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
