This is an automated email from Gerrit. Matthias Welwarsky ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3021
-- gerrit commit 177d923f3f1d48ec577778d543e3227e3d379875 Author: Matthias Welwarsky <[email protected]> Date: Thu Oct 15 18:09:33 2015 +0200 armv7a: use ctr.dminline and ctr.iminline for cache maintenance by MVA Caches can have different line lengths at different levels. ARM recommends using the information from ctr regarding the required minimal line lengths for cache maintenance by MVA. Change-Id: Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415 Signed-off-by: Matthias Welwarsky <[email protected]> diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 67d530a..69d4029 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -564,15 +564,28 @@ int armv7a_identify_cache(struct target *target) int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; - uint32_t cache_selected, clidr; + uint32_t cache_selected, clidr, ctr; uint32_t cache_i_reg, cache_d_reg; struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache); if (!armv7a->is_armv7r) armv7a_read_ttbcr(target); retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + goto done; + /* retrieve CTR + * mrc p15, 0, r0, c0, c0, 1 @ read ctr */ + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_MRC(15, 0, 0, 0, 0, 1), + &ctr); if (retval != ERROR_OK) goto done; + + cache->iminline = 4UL << (ctr & 0xf); + cache->dminline = 4UL << ((ctr & 0xf0000) >> 16); + LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32, + ctr, cache->iminline, cache->dminline); + /* retrieve CLIDR * mrc p15, 1, r0, c0, c0, 1 @ read clidr */ retval = dpm->instr_read_data_r0(dpm, diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 2ec5ba3..45c29a2 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -67,6 +67,8 @@ struct armv7a_cache_common { int ctype; struct armv7a_cachesize d_u_size; /* data cache */ struct armv7a_cachesize i_size; /* instruction cache */ + uint32_t dminline; /* minimum d-cache linelen */ + uint32_t iminline; /* minimum i-cache linelen */ int i_cache_enabled; int d_u_cache_enabled; int auto_cache_enabled; /* openocd automatic diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c index 3bcaddd..78cd284 100644 --- a/src/target/armv7a_cache.c +++ b/src/target/armv7a_cache.c @@ -139,7 +139,7 @@ static int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt, struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache; - uint32_t i, linelen = armv7a_cache->d_u_size.linelen; + uint32_t i, linelen = armv7a_cache->dminline; int retval; retval = armv7a_l1_d_cache_sanity_check(target); @@ -174,7 +174,7 @@ int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt, struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache; - uint32_t i, linelen = armv7a_cache->d_u_size.linelen; + uint32_t i, linelen = armv7a_cache->dminline; int retval; retval = armv7a_l1_d_cache_sanity_check(target); @@ -239,7 +239,7 @@ static int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt, struct arm_dpm *dpm = armv7a->arm.dpm; struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache; - uint32_t i, linelen = armv7a_cache->i_size.linelen; + uint32_t i, linelen = armv7a_cache->iminline; int retval; retval = armv7a_l1_i_cache_sanity_check(target); -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
