This is an automated email from Gerrit. Matthias Welwarsky ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3036
-- gerrit commit 436a87228dc84dfb9ed30baf36d4bac64ec791a3 Author: Matthias Welwarsky <[email protected]> Date: Sun Oct 18 14:15:12 2015 +0200 armv7a: fix instruction cache invalidate-all for SMP If the target is SMP enabled, use ICIALLUIS instead of ICIALLU to make sure the i-cache invalidate is visible to all cpus in the inner-shareable domain. Change-Id: Ia3cbf2b9cb1bda745523b256ed284261bfdf4f4a Signed-off-by: Matthias Welwarsky <[email protected]> diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c index 678a073..c27da68 100644 --- a/src/target/armv7a_cache.c +++ b/src/target/armv7a_cache.c @@ -306,11 +306,20 @@ int armv7a_l1_i_cache_inval_all(struct target *target) if (retval != ERROR_OK) goto done; - retval = dpm->instr_write_data_r0(dpm, - ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0); + if (target->smp) { + /* ICIALLUIS */ + retval = dpm->instr_write_data_r0(dpm, + ARMV4_5_MCR(15, 0, 0, 7, 1, 0), 0); + } else { + /* ICIALLU */ + retval = dpm->instr_write_data_r0(dpm, + ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0); + } + if (retval != ERROR_OK) goto done; + dpm->finish(dpm); return retval; done: -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
