This is an automated email from Gerrit. Alamy Liu ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3244
-- gerrit commit b2da8c0d94c1a4e6ed0bf374371f925b9caaa15f Author: Alamy Liu <[email protected]> Date: Tue Aug 11 11:16:16 2015 -0700 adi_v5: Update DP (Debug Port) registers defined in ADIv5.2. Note: WCR (Wire Control Register) is replaced by DLCR (Data Link Control Register). And only TURNROUND field is modifiable. Change-Id: Ic6b781b07c8eead8b0237d497846d0da060cb1ba Signed-off-by: Alamy Liu <[email protected]> diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c index f7a199c..a06645b 100644 --- a/src/target/adi_v5_swd.c +++ b/src/target/adi_v5_swd.c @@ -343,40 +343,26 @@ int dap_to_swd(struct target *target) return retval; } -COMMAND_HANDLER(handle_swd_wcr) +COMMAND_HANDLER(handle_swd_dlcr) { int retval; struct target *target = get_current_target(CMD_CTX); struct arm *arm = target_to_arm(target); struct adiv5_dap *dap = arm->dap; - uint32_t wcr; - unsigned trn, scale = 0; + uint32_t dlcr; + unsigned trn; switch (CMD_ARGC) { /* no-args: just dump state */ case 0: - /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */ - retval = dap_queue_dp_read(dap, DP_WCR, &wcr); - if (retval == ERROR_OK) - dap->ops->run(dap); + retval = dap_dp_read_atomic(dap, DP_DLCR, &dlcr); if (retval != ERROR_OK) { - LOG_ERROR("can't read WCR?"); + LOG_ERROR("can't read DLCR?"); return retval; } - command_print(CMD_CTX, - "turnaround=%" PRIu32 ", prescale=%" PRIu32, - WCR_TO_TRN(wcr), - WCR_TO_PRESCALE(wcr)); - return ERROR_OK; - - case 2: /* TRN and prescale */ - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale); - if (scale > 7) { - LOG_ERROR("prescale %d is too big", scale); - return ERROR_FAIL; - } - /* FALL THROUGH */ + command_print(CMD_CTX, "turnaround=%" PRIu32, DLCR_TO_TRN(dlcr)); + return ERROR_OK; case 1: /* TRN only */ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn); @@ -385,12 +371,25 @@ COMMAND_HANDLER(handle_swd_wcr) return ERROR_FAIL; } - wcr = ((trn - 1) << 8) | scale; + /* TURNROUND, bits[9:8]: Turnaround tristate period */ + dlcr = ((trn - 1) << 8); + + /* WIREMODE, bits[7:6] = 0b01: Synchronous, no oversampling */ + /* Other value are reserved */ + dlcr |= 0x1 << 6; + /* FIXME - * write WCR ... - * then, re-init adapter with new TRN + * write DLCR (Data link Control Register) ... + * then, re-init adapter with new Turnaround tristate period. */ - LOG_ERROR("can't yet modify WCR"); + /* + retval = dap_dp_write_atomic(dap, DP_DLCR, &dlcr); + if (retval != ERROR_OK) { + LOG_ERROR("can't write DLCR"); + return retval; + } + */ + LOG_ERROR("can't yet modify DLCR"); return ERROR_FAIL; default: /* too many arguments */ @@ -413,11 +412,11 @@ static const struct command_registration swd_commands[] = { .help = "declare a new SWD DAP" }, { - .name = "wcr", - .handler = handle_swd_wcr, + .name = "dlcr", + .handler = handle_swd_dlcr, .mode = COMMAND_ANY, - .help = "display or update DAP's WCR register", - .usage = "turnaround (1..4), prescale (0..7)", + .help = "display or update DAP's DLCR register", + .usage = "turnaround (1..4)", }, /* REVISIT -- add a command for SWV trace on/off */ diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 7c27d60..03d038c 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -5,6 +5,9 @@ * Copyright (C) 2008 by Spencer Oliver * * [email protected] * * * + * Copyright (C) 2014 by Alamy Liu * + * [email protected] * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -51,14 +54,17 @@ */ #define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */ #define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */ -#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */ +#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */ #define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */ #define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */ #define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */ -#define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */ +#define DP_TARGETSEL BANK_REG(0x0, 0xC) /* SWD/DPv2: wo */ +#define DP_DLCR BANK_REG(0x1, 0x4) /* SWD: rw */ +#define DP_TARGETID BANK_REG(0x2, 0x4) /* SWD/DPv2: ro */ +#define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* SWD/DPv2: ro */ +#define DP_DLPIDR BANK_REG(0x3, 0x4) /* SWD/DPv2: ro */ -#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */ -#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */ +#define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */ /* Fields of the DP's AP ABORT register */ #define DAPABORT (1UL << 0) -- ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. 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