This is an automated email from Gerrit. Alamy Liu ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3279
-- gerrit commit 1c8258a20f59e6d4c37b82c4e236885315bc3daf Author: Alamy Liu <[email protected]> Date: Wed Aug 12 16:06:02 2015 -0700 adi_v5(DEV): Implement dap_romtable_lookup_cs_component() Change-Id: I4b521647eb21350bb2aa4da1b06d08956b5e98b1 Signed-off-by: Alamy Liu <[email protected]> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index e70e017..2c9c5d6 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -2244,9 +2244,24 @@ static int aarch64_examine_first(struct target *target) retval = dap_get_debugbase(swjdp, 1, &dbgbase, &apid); if (retval != ERROR_OK) return retval; - /* Lookup 0x15 -- Processor DAP */ - retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15, - &armv8->debug_base, &coreidx); + + dbgbase &= ~0x3; + LOG_DEBUG("dbgbase=%x", dbgbase); + + + /* Alamy: ***** WARNING ***** + * Need to verify it's ROM Table (but it is) + * One should scan all APs (So far we know it's in AP1) + */ + dap_ap_select(swjdp, 1); /* Alamy(***** WARNING *****): Why it's in DAP1 ? */ + /* devtype(0x5,0x1) = Debug Logic - Processor */ + /* ARM Cortex-A57: PID=0x00000004002BBD07 --> 0x4BB, 0xD07 */ + /* ARM Cortex-A53: PID=0x00000004003BBD03 --> 0x4BB, 0xD03 */ + retval = dap_romtable_lookup_cs_component(swjdp, + dbgbase, 0x15, + JEP106_ARM, PID_PART_CORTEX_A53, + &coreidx, + &armv8->debug_base); if (retval != ERROR_OK) return retval; LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32, diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 05935f3..0d35781 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -882,6 +882,133 @@ int dap_lookup_cs_component(struct adiv5_ap *ap, return ERROR_OK; } +int dap_romtable_lookup_cs_component( + struct adiv5_dap *dap, + uintmax_t rombase, uint8_t l_devtype, + uint16_t l_jep106, uint16_t l_partnum, + int32_t *l_index, + uint32_t *found_base) +{ + int retval; + uint32_t entry_offset; /* Offset to walk through ROM Table */ + uint32_t romentry; + uintmax_t component_base; + struct _rom_entry entry; + + if (dap == NULL) return ERROR_FAIL; + if (found_base == NULL) return ERROR_OK; /* No need to continue */ + + /* Clear to zero so we know the component is found or not later */ + *found_base = 0x0; + + /* + * Now we read ROM table entries until we + * reach the end of the ROM Table (0xF00) + * or hit a blank entry (0x00000000) + */ + for (entry_offset = 0; entry_offset < 0xF00 ; entry_offset += 4) { + retval = mem_ap_read_atomic_u32(dap, + rombase | entry_offset, + &romentry); + if (retval != ERROR_OK) + continue; + + LOG_DEBUG("---- Entry[0x%03X/0x%" PRIXMAX "] = 0x%08x %s", + entry_offset, rombase, romentry, + (romentry==0x0 ? "(end of table)" : "")); + + if (romentry == 0x0) /* Table end marker */ + break; + + + /* decode entry fields + * IHI0031C: Table 10-2 Format of a ROM Table entry + */ + entry.addr_ofst = romentry & (0xFFFFF << 12); /* signed */ + entry.power_domain_id = (romentry & (0x1F << 4)) >> 4; + entry.power_domain_id_valid = (romentry & ( 0x1 << 2)) >> 2; + entry.format = (romentry & ( 0x1 << 1)) >> 1; + entry.present = (romentry & ( 0x1 << 0)) >> 0; + + /* 10.2.2 Empty entries and the end of the ROM Table + * When scanning the ROM Table, an entry marked as + * not present must be skipped. However you must not assume + * that an entry that is marked as not present represents + * the end of the ROM Table + */ + if (! entry.present) /* Empty entry */ + continue; + + if (! entry.format) /* Not a 32-bit ROM entry format */ + continue; + + LOG_DEBUG("ofst=0x%08x, pwrID=0x%x(valid=%d)", + entry.addr_ofst, + entry.power_domain_id, entry.power_domain_id_valid); + + + /* 10.2.1 Component descriptions and the component base address */ + /* Component_Base = ROM_Base + Address offset */ + component_base = rombase + entry.addr_ofst; +// LOG_DEBUG("component_base(last 4KB)=0x%.16" PRIxMAX, component_base); + + retval = mem_ap_read_pid_cid(dap, component_base, + &(entry.PID), &(entry.CID)); + if (! is_pid_cid_valid(entry.PID, entry.CID)) + continue; + + /* find the 1st 4KB address (true component base address ) */ + component_base -= 0x1000 * (get_pid_4k_count(entry.PID) - 1); + LOG_DEBUG("base(1st 4KB)=0x%.16" PRIxMAX, component_base); + + switch (get_cid_class(entry.CID)) + { + uint32_t devtype; + case CC_ROM: /* ROM Table */ + retval = dap_romtable_lookup_cs_component(dap, + component_base, l_devtype, + l_jep106, l_partnum, + l_index, + found_base); + if ((retval == ERROR_OK) || (retval == ERROR_FAIL)) + return ERROR_OK; + /* Let's continue if component not found */ + break; + + case CC_DEBUG: /* Debug (CoreSight) component */ +// uint32_t devtype; + retval = mem_ap_read_atomic_u32(dap, component_base | 0xFCC, &devtype); + if (retval != ERROR_OK) return retval; + + /* Matching devtype & PID */ + if ((devtype & 0xFF) != l_devtype) continue; + if (pid_get_jep106(entry.PID) != l_jep106) continue; + if (pid_get_partnum(entry.PID) != l_partnum) continue; +// if ((*l_index)--) continue; + + /* Found the component */ + if ( !((*l_index)--) ) { + *found_base = component_base; + return ERROR_OK; + } + break; + + default: + /* We are not interested in other classes + CC_VERIFICATION: Generic verification component + CC_PTB: Peripheral Test Block (PTB) + CC_DESS: OptimoDE Data Engine SubSystem component + CC_IP: Generic IP component + CC_PCELL: PrimeCell peripheral + */ + break; + } /* End of switch (cid class) */ + } /* End of for(entry_offset) */ + + /* Woops, component not found */ + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; +} + /* The designer identity code is encoded as: * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1. * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index ffbfdc2..af694a6 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -156,6 +156,20 @@ #define IDR_REV_SHIFT (28) #define IDR_REV_MASK (0xF << IDR_REV_SHIFT) +typedef enum cid_class { /* CID[15:12] */ + CC_VERIFICATION = 0x0, /* Generic verification component */ + CC_ROM = 0x1, /* ROM Table */ + CC_DEBUG = 0x9, /* Debug (CoreSight) component */ + CC_PTB = 0xB, /* Peripheral Test Block (PTB) */ + CC_DESS = 0xD, /* OptimoDE Data Engine SubSystem component */ + CC_IP = 0xE, /* Generic IP component */ + CC_PCELL = 0xF /* PrimeCell peripheral */ +} cid_class_t; + +#define JEP106_ARM (0x43B) +#define PID_PART_CORTEX_A57 (0xD07) +#define PID_PART_CORTEX_A53 (0xD03) + /* Fields of the MEM-AP's IDR register */ #define IDR_REV (0xFUL << 28) #define IDR_JEP106 (0x7FFUL << 17) @@ -313,6 +327,67 @@ struct dap_ops { int (*sync)(struct adiv5_dap *dap); }; +typedef struct _rom_entry { + int32_t addr_ofst; /* Relative base address of the component (signed) */ + + unsigned int power_domain_id:5; /* Power domain of the component */ + bool power_domain_id_valid:1; /* Indicates if the Power domain ID is valid */ + bool format:1; /* 32-bit ROM Table format */ + bool present:1; /* Entry present */ + + uint64_t PID; /* bits[7:0] of each PIDR */ + uint32_t CID; /* bits[7:0] of each CIDR */ + +#if 0 + /* WARNING: not sharing(union) with PID. + * C compiler does NOT guarantee bit fields mapping. + */ + struct _pid { /* bit fields of PID */ + uint8_t 4kb_log2_count:4; + uint8_t jep106_cont:4; + uint8_t revand:4; + uint8_t cust:4; + uint8_t rev:4; + uint8_t is_jep106:1; + uint8_t jep106_id:7; + uint16_t partnum:12; + } pid; +#endif + +} rom_entry_t; + + +/* NOTE: JEP106 Continuation code & ID code + * For easy understanding (i.e.: ARM(0x4, 0x3B) -> 0x43B) + * Use 8-bit to hold 7-bit ID code (bit[7] is not used). + * Continuation code will be at bit[12:9] + * Thus, JEP106_ARM would be 0x43B + */ +/* + * PID[35:32]: JEP106 Continuation code (ARM is 0x4) + * PID[19] : Uses JEP106 ID code (should be 0b1) + * PID[18:12]: JEP106 ID code (ARM is 0x3B) + */ +static inline uint16_t pid_get_jep106(uint64_t pid) +{ + uint16_t jep106; + + jep106 = (((pid >> 32) & 0x0F) << 8); /* bit[35:32] */ + jep106 |= ((pid >> 12) & 0x7F); /* bit[18:12] */ + + return jep106; /* jep106 == 0x43B for ARM */ +} + +/* bit[11:0] of PID */ +static inline uint16_t pid_get_partnum(uint64_t pid) +{ + return (uint16_t)(pid & 0x0FFF); +} + + +extern void jtag_dump_queue(const char *func, int line); + + /* * Access Port classes (IDR[16:13]) */ @@ -591,6 +666,13 @@ static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num) /* Lookup CoreSight component */ int dap_lookup_cs_component(struct adiv5_ap *ap, uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx); +/* Look up CoreSight component in ROM Table */ +int dap_romtable_lookup_cs_component( + struct adiv5_dap *dap, + uintmax_t rombase, uint8_t l_devtype, + uint16_t l_jep106, uint16_t l_partnum, + int32_t *l_index, + uint32_t *found_base); struct target; -- ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140 _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
