This is an automated email from Gerrit. Alamy Liu ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3253
-- gerrit commit 8b93eac4875661a9b0cde821a20bed8d580ae922 Author: Alamy Liu <[email protected]> Date: Tue Aug 11 16:01:53 2015 -0700 adi_v5: Synchronize CSW register's fields definition format: CSW_<field>_<value> i.e.: CSW_8BIT -> CSW_SIZE_8BIT Seperate word with '_' i.e.: CSW_SPIDEN -> CSW_SPID_EN TAB to replace space Note CSW register's bit definition is vary from AHB-AP, APB-AP, and AXI-AP. There are some common fields, but others seem to be specific for AHB-AP bus. If it does not work on other MEM-AP bus (APB or AXI), review the settings in dap_setup_accessport_csw() which sets CSW_MASTER_DEBUG and CSW_HPROT that does not seems to be available in other MEM-AP bus. Change-Id: I0cbca7daecb8d718fbacff908c25de5039f960d0 Signed-off-by: Alamy Liu <[email protected]> diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index c925450..a564c79 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -97,7 +97,7 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw) { - csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT | + csw = csw | CSW_DBG_SW_ENABLE | CSW_MASTER_DEBUG | CSW_HPROT | ap->csw_default; if (csw != ap->csw_value) { @@ -171,7 +171,7 @@ int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address, /* Use banked addressing (REG_BDx) to avoid some link traffic * (updating TAR) when reading several consecutive addresses. */ - retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF, + retval = mem_ap_setup_transfer(ap, CSW_SIZE_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); if (retval != ERROR_OK) return retval; @@ -222,7 +222,7 @@ int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address, /* Use banked addressing (REG_BDx) to avoid some link traffic * (updating TAR) when writing several consecutive addresses. */ - retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF, + retval = mem_ap_setup_transfer(ap, CSW_SIZE_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); if (retval != ERROR_OK) return retval; @@ -289,13 +289,13 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz * address increment. */ if (size == 4) { - csw_size = CSW_32BIT; + csw_size = CSW_SIZE_32BIT; addr_xor = 0; } else if (size == 2) { - csw_size = CSW_16BIT; + csw_size = CSW_SIZE_16BIT; addr_xor = dap->ti_be_32_quirks ? 2 : 0; } else if (size == 1) { - csw_size = CSW_8BIT; + csw_size = CSW_SIZE_8BIT; addr_xor = dap->ti_be_32_quirks ? 3 : 0; } else { return ERROR_TARGET_UNALIGNED_ACCESS; @@ -414,11 +414,11 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint * so avoid them. */ if (size == 4) - csw_size = CSW_32BIT; + csw_size = CSW_SIZE_32BIT; else if (size == 2) - csw_size = CSW_16BIT; + csw_size = CSW_SIZE_16BIT; else if (size == 1) - csw_size = CSW_8BIT; + csw_size = CSW_SIZE_8BIT; else return ERROR_TARGET_UNALIGNED_ACCESS; @@ -685,7 +685,7 @@ int mem_ap_init(struct adiv5_ap *ap) int retval; struct adiv5_dap *dap = ap->dap; - retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0); + retval = mem_ap_setup_transfer(ap, CSW_SIZE_8BIT | CSW_ADDRINC_PACKED, 0); if (retval != ERROR_OK) return retval; diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 8af9193..11a1b11 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -107,21 +107,30 @@ #define AP_REG_IDR 0xFC /* RO: Identification Register */ /* Fields of the MEM-AP's CSW register */ -#define CSW_8BIT 0 -#define CSW_16BIT 1 -#define CSW_32BIT 2 -#define CSW_ADDRINC_MASK (3UL << 4) -#define CSW_ADDRINC_OFF 0UL -#define CSW_ADDRINC_SINGLE (1UL << 4) -#define CSW_ADDRINC_PACKED (2UL << 4) -#define CSW_DEVICE_EN (1UL << 6) -#define CSW_TRIN_PROG (1UL << 7) -#define CSW_SPIDEN (1UL << 23) +#define CSW_SIZE_MASK (7UL << 0) +#define CSW_SIZE_8BIT (0) /* Byte ( 8-bits) */ +#define CSW_SIZE_16BIT (1) /* Halfword ( 16-bits) */ +#define CSW_SIZE_32BIT (2) /* Word ( 32-bits) */ +#define CSW_SIZE_64BIT (3) /* Doubleword ( 64-bits) */ +#define CSW_SIZE_128BIT (4) /* - (128-bits) */ +#define CSW_SIZE_256BIT (5) /* - (256-bits) */ + +#define CSW_ADDRINC_MASK (3UL << 4) +#define CSW_ADDRINC_OFF (0UL << 4) +#define CSW_ADDRINC_SINGLE (1UL << 4) +#define CSW_ADDRINC_PACKED (2UL << 4) +#define CSW_DEVICE_EN (1UL << 6) +#define CSW_TRIN_PROG (1UL << 7) /* Transfer in Progress */ +#define CSW_MODE_MASK (0xF << 8) +#define CSW_MODE_BASIC (0UL << 8) +#define CSW_MODE_BARRIER (1UL << 8) +#define CSW_TYPE_MASK (0xF << 12) +#define CSW_SPID_EN (1UL << 23) /* 30:24 - implementation-defined! */ -#define CSW_HPROT (1UL << 25) /* ? */ -#define CSW_MASTER_DEBUG (1UL << 29) /* ? */ -#define CSW_SPROT (1UL << 30) -#define CSW_DBGSWENABLE (1UL << 31) +#define CSW_HPROT (1UL << 25) /* ? */ +#define CSW_MASTER_DEBUG (1UL << 29) /* ? */ +#define CSW_SPROT (1UL << 30) +#define CSW_DBG_SW_ENABLE (1UL << 31) /* Fields of the MEM-AP's IDR register */ #define IDR_REV (0xFUL << 28) -- ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. 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