This is an automated email from Gerrit. Alamy Liu ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3263
-- gerrit commit ef4c3d25ae5c48af8a127be5af8e6c45e8d2c2ba Author: Alamy Liu <[email protected]> Date: Mon Aug 17 14:03:18 2015 -0700 64-bit: use uint64_t(uintmax_t) for interface functions (armv8) "target" object uses "struct target_type" to hook with target functions. It has problem when 64-bit comes in, as the parameters (interface) has to be changed to hold 64-bit information. OOP would be the solution for this situation, but it need to rewirte a lot of code. Inherit OOP's idea, I hereby separate 64-bit functions from 32-bit ones by creating another "target_type_64" structure. The benefits are: - Doesn't have to modify original target codes. (i.e.: arm11, arm920t, nds32, ...) Hence, saving the time for testing. - When the time comes to change the structure to OOP, the convertion would be more straight forward. Change-Id: Ic1fa7f0d2f9df8450fdbfdd9a63d4b5c6a7a4d95 Signed-off-by: Alamy Liu <[email protected]> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 7a3d134..33fd966 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -26,6 +26,7 @@ #include "register.h" #include "target_request.h" #include "target_type.h" +#include "target_type64.h" #include "arm_opcodes.h" #include <helper/time_support.h> @@ -42,7 +43,7 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); static int aarch64_mmu(struct target *target, int *enabled); static int aarch64_virt2phys(struct target *target, - target_ulong virt, target_ulong *phys); + uint64_t virt, uint64_t *phys); static int aarch64_read_apb_ab_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer); static int aarch64_instr_write_data_r0(struct arm_dpm *dpm, @@ -1030,7 +1031,7 @@ static int aarch64_restore_smp(struct target *target, int handle_breakpoints) } static int aarch64_resume(struct target *target, int current, - target_ulong address, int handle_breakpoints, int debug_execution) + uint64_t address, int handle_breakpoints, int debug_execution) { int retval = 0; uint64_t addr = address; @@ -1057,11 +1058,11 @@ static int aarch64_resume(struct target *target, int current, if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - LOG_DEBUG("target resumed at 0x%" PRIu64, addr); + LOG_DEBUG("target resumed at 0x%.16" PRIX64, addr); } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); - LOG_DEBUG("target debug resumed at 0x%" PRIu64, addr); + LOG_DEBUG("target debug resumed at 0x%.16" PRIX64, addr); } return ERROR_OK; @@ -1158,7 +1159,7 @@ static int aarch64_post_debug_entry(struct target *target) return ERROR_OK; } -static int aarch64_step(struct target *target, int current, target_ulong address, +static int aarch64_step(struct target *target, int current, uint64_t address, int handle_breakpoints) { struct armv8_common *armv8 = target_to_armv8(target); @@ -1284,7 +1285,7 @@ static int aarch64_set_breakpoint(struct target *target, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; - LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" PRIXX, brp_i, + LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%.16" PRIx64, brp_i, brp_list[brp_i].control, brp_list[brp_i].value); @@ -1362,9 +1363,8 @@ static int aarch64_set_context_breakpoint(struct target *target, brp_list[brp_i].control); if (retval != ERROR_OK) return retval; - LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" PRIXX, brp_i, - brp_list[brp_i].control, - brp_list[brp_i].value); + LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%.16" PRIx64, + brp_i, brp_list[brp_i].control, brp_list[brp_i].value); return ERROR_OK; } @@ -1470,8 +1470,8 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } - LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" PRIXX, brp_i, - brp_list[brp_i].control, brp_list[brp_i].value); + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%.16" PRIx64, + brp_i, brp_list[brp_i].control, brp_list[brp_i].value); brp_list[brp_i].used = 0; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; @@ -1484,8 +1484,8 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } - LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" PRIXX, brp_j, - brp_list[brp_j].control, brp_list[brp_j].value); + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%.16" PRIx64, + brp_j, brp_list[brp_j].control, brp_list[brp_j].value); brp_list[brp_j].used = 0; brp_list[brp_j].value = 0; brp_list[brp_j].control = 0; @@ -1504,8 +1504,8 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } - LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" PRIXX, brp_i, - brp_list[brp_i].control, brp_list[brp_i].value); + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%.16" PRIx64, + brp_i, brp_list[brp_i].control, brp_list[brp_i].value); brp_list[brp_i].used = 0; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; @@ -1917,15 +1917,15 @@ error_free_buff_r: } static int aarch64_read_phys_memory(struct target *target, - target_ulong address, uint32_t size, + uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct armv8_common *armv8 = target_to_armv8(target); struct adiv5_dap *swjdp = armv8->arm.dap; int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; - LOG_DEBUG("Reading memory at real address 0x%" PRIXX "; size %" PRId32 "; count %" PRId32, - address, size, count); + LOG_DEBUG("Reading memory at real address 0x%.16" PRIX64 "; size %" PRId32 + "; count %" PRId32, address, size, count); if (count && buffer) { @@ -1944,18 +1944,18 @@ static int aarch64_read_phys_memory(struct target *target, return retval; } -static int aarch64_read_memory(struct target *target, target_ulong address, +static int aarch64_read_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int mmu_enabled = 0; - target_ulong virt, phys; + uint64_t virt, phys; int retval; struct armv8_common *armv8 = target_to_armv8(target); struct adiv5_dap *swjdp = armv8->arm.dap; uint8_t apsel = swjdp->apsel; /* aarch64 handles unaligned memory access */ - LOG_DEBUG("Reading memory at address 0x%" PRIXX "; size %" PRId32 + LOG_DEBUG("Reading memory at address 0x%.16" PRIX64 "; size %" PRId32 "; count %" PRId32, address, size, count); /* determine if MMU was enabled on target stop */ @@ -1972,8 +1972,8 @@ static int aarch64_read_memory(struct target *target, target_ulong address, if (retval != ERROR_OK) return retval; - LOG_DEBUG("Reading at virtual address. Translating v:0x%" - PRIXX " to r:0x%" PRIXX, virt, phys); + LOG_DEBUG("Reading at virtual address. Translating virt:0x%.16" + PRIX64 " to phys:0x%.16" PRIX64, virt, phys); address = phys; } retval = aarch64_read_phys_memory(target, address, size, count, @@ -1996,7 +1996,7 @@ static int aarch64_read_memory(struct target *target, target_ulong address, } static int aarch64_write_phys_memory(struct target *target, - target_ulong address, uint32_t size, + uint64_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct armv8_common *armv8 = target_to_armv8(target); @@ -2004,8 +2004,8 @@ static int aarch64_write_phys_memory(struct target *target, int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; - LOG_DEBUG("Writing memory to real address 0x%" PRIXX "; size %" PRId32 "; count %" PRId32, address, - size, count); + LOG_DEBUG("Writing memory to real address 0x%.16" PRIX64 "; size %" PRId32 + "; count %" PRId32, address, size, count); if (count && buffer) { @@ -2083,18 +2083,18 @@ static int aarch64_write_phys_memory(struct target *target, return retval; } -static int aarch64_write_memory(struct target *target, target_ulong address, +static int aarch64_write_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { int mmu_enabled = 0; - target_ulong virt, phys; + uint64_t virt, phys; int retval; struct armv8_common *armv8 = target_to_armv8(target); struct adiv5_dap *swjdp = armv8->arm.dap; uint8_t apsel = swjdp->apsel; /* aarch64 handles unaligned memory access */ - LOG_DEBUG("Writing memory at address 0x%" PRIXX "; size %" PRId32 + LOG_DEBUG("Writing memory at address 0x%.16" PRIX64 "; size %" PRId32 "; count %" PRId32, address, size, count); /* determine if MMU was enabled on target stop */ @@ -2105,16 +2105,16 @@ static int aarch64_write_memory(struct target *target, target_ulong address, } if (armv8->memory_ap_available && (apsel == armv8->memory_ap)) { - LOG_DEBUG("Writing memory to address 0x%" PRIXX "; size %" - PRId32 "; count %" PRId32, address, size, count); + LOG_DEBUG("Writing memory to address 0x%.16" PRIX64 "; size %" + PRId32 "; count %" PRId32, address, size, count); if (mmu_enabled) { virt = address; retval = aarch64_virt2phys(target, virt, &phys); if (retval != ERROR_OK) return retval; - LOG_DEBUG("Writing to virtual address. Translating v:0x%" - PRIXX " to r:0x%" PRIXX, virt, phys); + LOG_DEBUG("Writing to virtual address. Translating virt:0x%.16" + PRIX64 " to phys:0x%.16" PRIX64, virt, phys); address = phys; } retval = aarch64_write_phys_memory(target, address, size, @@ -2404,8 +2404,8 @@ static int aarch64_mmu(struct target *target, int *enabled) return ERROR_OK; } -static int aarch64_virt2phys(struct target *target, target_ulong virt, - target_ulong *phys) +static int aarch64_virt2phys(struct target *target, uint64_t virt, + uint64_t *phys) { int retval = ERROR_FAIL; struct armv8_common *armv8 = target_to_armv8(target); @@ -2562,7 +2562,7 @@ static const struct command_registration aarch64_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct target_type aarch64_target = { +struct target_type_64 aarch64_target = { .name = "aarch64", .poll = aarch64_poll, @@ -2581,10 +2581,12 @@ struct target_type aarch64_target = { .read_memory = aarch64_read_memory, .write_memory = aarch64_write_memory, +#if 0 /* Alamy: Enable later */ .checksum_memory = arm_checksum_memory, .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, +#endif .add_breakpoint = aarch64_add_breakpoint, .add_context_breakpoint = aarch64_add_context_breakpoint, diff --git a/src/target/aarch64.h b/src/target/aarch64.h index 9f71f90..bd5e6b8 100644 --- a/src/target/aarch64.h +++ b/src/target/aarch64.h @@ -39,7 +39,7 @@ struct aarch64_brp { int used; int type; - target_ulong value; + uint64_t value; uint32_t control; uint8_t BRPn; }; diff --git a/src/target/armv8.c b/src/target/armv8.c index e98eacb..bb3f85a 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -60,7 +60,7 @@ static int armv8_read_core_reg(struct target *target, struct reg *r, #if 0 static int armv8_write_core_reg(struct target *target, struct reg *r, - int num, enum arm_mode mode, target_ulong value) + int num, enum arm_mode mode, uint64_t value) { int retval; struct arm_reg *armv8_core_reg; @@ -226,8 +226,8 @@ done: } /* V8 method VA TO PA */ -int armv8_mmu_translate_va_pa(struct target *target, target_ulong va, - target_ulong *val, int meminfo) +int armv8_mmu_translate_va_pa(struct target *target, uint64_t va, + uint64_t *val, int meminfo) { return ERROR_OK; } diff --git a/src/target/armv8.h b/src/target/armv8.h index 536fc6c..8ca1831 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -116,7 +116,7 @@ struct armv8_mmu_common { uint32_t ttbr0_mask;/* masked to be used */ uint32_t os_border; - int (*read_physical_memory)(struct target *target, target_ulong address, + int (*read_physical_memory)(struct target *target, uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer); struct armv8_cache_common armv8_cache; uint32_t mmu_enabled; @@ -193,8 +193,8 @@ target_to_armv8(struct target *target) int armv8_arch_state(struct target *target); int armv8_identify_cache(struct target *target); int armv8_init_arch_info(struct target *target, struct armv8_common *armv8); -int armv8_mmu_translate_va_pa(struct target *target, target_ulong va, - target_ulong *val, int meminfo); +int armv8_mmu_translate_va_pa(struct target *target, uint64_t va, + uint64_t *val, int meminfo); int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val); int armv8_handle_cache_info_command(struct command_context *cmd_ctx, diff --git a/src/target/target_type64.h b/src/target/target_type64.h new file mode 100644 index 0000000..66c3fb0 --- /dev/null +++ b/src/target/target_type64.h @@ -0,0 +1,272 @@ +/*************************************************************************** + * Copyright (C) 2015 by Alamy Liu * + * [email protected] * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + ***************************************************************************/ + +#ifndef __TARGET_TYPE_64_H_ +#define __TARGET_TYPE_64_H_ + +#include <jim-nvp.h> + +struct target; + +/* + * Extention of target_type for 64-bit target(s) + */ +struct target_type_64 { + /** + * Name of this type of target. Do @b not access this + * field directly, use target_type_name() instead. + */ + const char *name; + + /* poll current target status */ + int (*poll)(struct target *target); + /* Invoked only from target_arch_state(). + * Issue USER() w/architecture specific status. */ + int (*arch_state)(struct target *target); + + /* target request support */ + int (*target_request_data)(struct target *target, uint32_t size, uint8_t *buffer); + + /* halt will log a warning, but return ERROR_OK if the target is already halted. */ + int (*halt)(struct target *target); + int (*resume)(struct target *target, int current, uint64_t address, + int handle_breakpoints, int debug_execution); + int (*step)(struct target *target, int current, uint64_t address, + int handle_breakpoints); + + /* target reset control. assert reset can be invoked when OpenOCD and + * the target is out of sync. + * + * A typical example is that the target was power cycled while OpenOCD + * thought the target was halted or running. + * + * assert_reset() can therefore make no assumptions whatsoever about the + * state of the target + * + * Before assert_reset() for the target is invoked, a TRST/tms and + * chain validation is executed. TRST should not be asserted + * during target assert unless there is no way around it due to + * the way reset's are configured. + * + */ + int (*assert_reset)(struct target *target); + /** + * The implementation is responsible for polling the + * target such that target->state reflects the + * state correctly. + * + * Otherwise the following would fail, as there will not + * be any "poll" invoked inbetween the "reset run" and + * "halt". + * + * reset run; halt + */ + int (*deassert_reset)(struct target *target); + int (*soft_reset_halt)(struct target *target); + + /** + * Target register access for GDB. Do @b not call this function + * directly, use target_get_gdb_reg_list() instead. + * + * Danger! this function will succeed even if the target is running + * and return a register list with dummy values. + * + * The reason is that GDB connection will fail without a valid register + * list, however it is after GDB is connected that monitor commands can + * be run to properly initialize the target + */ + int (*get_gdb_reg_list)(struct target *target, struct reg **reg_list[], + int *reg_list_size, enum target_register_class reg_class); + + /* target memory access + * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) + * count: number of items of <size> + */ + + /** + * Target memory read callback. Do @b not call this function + * directly, use target_read_memory() instead. + */ + int (*read_memory)(struct target *target, uint64_t address, + uint32_t size, uint32_t count, uint8_t *buffer); + /** + * Target memory write callback. Do @b not call this function + * directly, use target_write_memory() instead. + */ + int (*write_memory)(struct target *target, uint64_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); + + /* Default implementation will do some fancy alignment to improve performance, target can override */ + int (*read_buffer)(struct target *target, uint64_t address, + uint32_t size, uint8_t *buffer); + + /* Default implementation will do some fancy alignment to improve performance, target can override */ + int (*write_buffer)(struct target *target, uint64_t address, + uint32_t size, const uint8_t *buffer); + + int (*checksum_memory)(struct target *target, uint64_t address, + uint32_t count, uint32_t *checksum); + int (*blank_check_memory)(struct target *target, uint64_t address, + uint32_t count, uint32_t *blank); + + /* + * target break-/watchpoint control + * rw: 0 = write, 1 = read, 2 = access + * + * Target must be halted while this is invoked as this + * will actually set up breakpoints on target. + * + * The breakpoint hardware will be set up upon adding the + * first breakpoint. + * + * Upon GDB connection all breakpoints/watchpoints are cleared. + */ + int (*add_breakpoint)(struct target *target, struct breakpoint *breakpoint); + int (*add_context_breakpoint)(struct target *target, struct breakpoint *breakpoint); + int (*add_hybrid_breakpoint)(struct target *target, struct breakpoint *breakpoint); + + /* remove breakpoint. hw will only be updated if the target + * is currently halted. + * However, this method can be invoked on unresponsive targets. + */ + int (*remove_breakpoint)(struct target *target, struct breakpoint *breakpoint); + + /* add watchpoint ... see add_breakpoint() comment above. */ + int (*add_watchpoint)(struct target *target, struct watchpoint *watchpoint); + + /* remove watchpoint. hw will only be updated if the target + * is currently halted. + * However, this method can be invoked on unresponsive targets. + */ + int (*remove_watchpoint)(struct target *target, struct watchpoint *watchpoint); + + /* Find out just hit watchpoint. After the target hits a watchpoint, the + * information could assist gdb to locate where the modified/accessed memory is. + */ + int (*hit_watchpoint)(struct target *target, struct watchpoint **hit_watchpoint); + + /** + * Target algorithm support. Do @b not call this method directly, + * use target_run_algorithm() instead. + */ + int (*run_algorithm)(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_params, + struct reg_param *reg_param, uint64_t entry_point, + uint64_t exit_point, int timeout_ms, void *arch_info); + int (*start_algorithm)(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_params, + struct reg_param *reg_param, uint64_t entry_point, + uint64_t exit_point, void *arch_info); + int (*wait_algorithm)(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_params, + struct reg_param *reg_param, uint64_t exit_point, + int timeout_ms, void *arch_info); + + const struct command_registration *commands; + + /* called when target is created */ + int (*target_create)(struct target *target, Jim_Interp *interp); + + /* called for various config parameters */ + /* returns JIM_CONTINUE - if option not understood */ + /* otherwise: JIM_OK, or JIM_ERR, */ + int (*target_jim_configure)(struct target *target, Jim_GetOptInfo *goi); + + /* target commands specifically handled by the target */ + /* returns JIM_OK, or JIM_ERR, or JIM_CONTINUE - if option not understood */ + int (*target_jim_commands)(struct target *target, Jim_GetOptInfo *goi); + + /** + * This method is used to perform target setup that requires + * JTAG access. + * + * This may be called multiple times. It is called after the + * scan chain is initially validated, or later after the target + * is enabled by a JRC. It may also be called during some + * parts of the reset sequence. + * + * For one-time initialization tasks, use target_was_examined() + * and target_set_examined(). For example, probe the hardware + * before setting up chip-specific state, and then set that + * flag so you don't do that again. + */ + int (*examine)(struct target *target); + + /* Set up structures for target. + * + * It is illegal to talk to the target at this stage as this fn is invoked + * before the JTAG chain has been examined/verified + * */ + int (*init_target)(struct command_context *cmd_ctx, struct target *target); + + /** + * Free all the resources allocated by the target. + * + * @param target The target to deinit + */ + void (*deinit_target)(struct target *target); + + /* translate from virtual to physical address. Default implementation is successful + * no-op(i.e. virtual==physical). + */ + int (*virt2phys)(struct target *target, uint64_t address, uint64_t *physical); + + /* read directly from physical memory. caches are bypassed and untouched. + * + * If the target does not support disabling caches, leaving them untouched, + * then minimally the actual physical memory location will be read even + * if cache states are unchanged, flushed, etc. + * + * Default implementation is to call read_memory. + */ + int (*read_phys_memory)(struct target *target, uint64_t phys_address, + uint32_t size, uint32_t count, uint8_t *buffer); + + /* + * same as read_phys_memory, except that it writes... + */ + int (*write_phys_memory)(struct target *target, uint64_t phys_address, + uint32_t size, uint32_t count, const uint8_t *buffer); + + int (*mmu)(struct target *target, int *enabled); + + /* after reset is complete, the target can check if things are properly set up. + * + * This can be used to check if e.g. DCC memory writes have been enabled for + * arm7/9 targets, which they really should except in the most contrived + * circumstances. + */ + int (*check_reset)(struct target *target); + + /* get GDB file-I/O parameters from target + */ + int (*get_gdb_fileio_info)(struct target *target, struct gdb_fileio_info *fileio_info); + + /* pass GDB file-I/O response to target + */ + int (*gdb_fileio_end)(struct target *target, int retcode, int fileio_errno, bool ctrl_c); + + /* do target profiling + */ + int (*profiling)(struct target *target, uintmax_t *samples, + uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds); +}; + +#endif /* __TARGET_TYPE_64_H_ */ -- ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. 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