This is an automated email from Gerrit. Alamy Liu ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3316
-- gerrit commit cfbbb5e9109eb946ec754ee0207640deb3260427 Author: Alamy Liu <[email protected]> Date: Wed Oct 14 09:38:10 2015 -0700 arm_dpm: Add MRS/MSR functions for ARMv8 ARMv8 does not use MRC/MCR instructions but MRS/MSR to load/save register values. The encodings are also different. Change-Id: I7121ddfab87578bd8769c75d6acdb2aa0d87ceb4 Signed-off-by: Alamy Liu <[email protected]> diff --git a/src/target/arm.h b/src/target/arm.h index 1a2fe85..021ced3 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -169,6 +169,10 @@ struct arm { uint32_t CRn, uint32_t CRm, uint32_t value); + /* ARMv8 specific instruction: MRS/MSR */ + int (*mrs)(struct target *target, uint32_t itr, uint64_t *value); /* R */ + int (*msr)(struct target *target, uint32_t itr, uint64_t value); /* W */ + void *arch_info; /** For targets conforming to ARM Debug Interface v5, diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 7484073..083c0e5 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -102,6 +102,55 @@ static int dpm_mcr(struct target *target, int cpnum, return retval; } +/* ARMv8 specific function + * MRS: Read register value through general purpose register + * MSR: Write value to register through general purpose register + * Note: + * - 64-bit general registers are accessed by + * read_current_registers_64() + * write_dirty_registers_64() + * - Although most registers are 32-bit in AArch64 mode, + * MRS/MSR deals with 64-bit data. 32-bit value could just ignore + * upper 32-bit data in 64-bit value. + * - 32-bit safe + * Read: It's safe to read 64-bit data in aarch64_read_dcc_64() + * H9.2.6 DBGDTRRX_EL0 + * Reads of this register return the last value written to DTRRX + * and do not change RXfull + * Write: (Alamy: ***** WARNING: examine *****) + * + * + */ +static int dpm_mrs(struct target *target, uint32_t itr, uint64_t *value) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval; + + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) return retval; + + retval = dpm->instr_read_data_x0(dpm, itr, value); + + /* (void) */ dpm->finish(dpm); + return retval; +} + +static int dpm_msr(struct target *target, uint32_t itr, uint64_t value) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval; + + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) return retval; + + retval = dpm->instr_write_data_x0(dpm, itr, value); + + /* (void) */ dpm->finish(dpm); + return retval; +} + /*----------------------------------------------------------------------*/ /* @@ -1231,6 +1280,10 @@ int arm_dpm_setup(struct arm_dpm *dpm) /* coprocessor access setup */ arm->mrc = dpm_mrc; arm->mcr = dpm_mcr; + if (is_aarch64(target)) { + arm->mrs = dpm_mrs; + arm->msr = dpm_msr; + } /* breakpoint setup -- optional until it works everywhere */ if (!TYPE_FUNC_VALIDATE(add_breakpoint)) { -- ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140 _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
