This is an automated email from Gerrit. Eric Katzfey ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3706
-- gerrit commit cf699f787d6b6b56c7fc2aae9b675a7cc79a3da3 Author: Eric Katzfey <[email protected]> Date: Wed Aug 17 16:06:45 2016 -0700 cortex_a: Added support for Qualcomm Krait processors in examine Cleaned up to check to find out whether we need to unlock the debug registers and added a new check for Qualcomm Krait processors. Change-Id: I032c3a3dfaa4d59aaa2603e017c132177c20ca74 Signed-off-by: Eric Katzfey <[email protected]> diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index d1590f6..1ee4d64 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2955,7 +2955,8 @@ static int cortex_a_examine_first(struct target *target) struct adiv5_dap *swjdp = armv7a->arm.dap; int i; int retval = ERROR_OK; - uint32_t didr, ctypr, ttypr, cpuid, dbg_osreg; + uint32_t didr, ctypr, ttypr, cpuid, dbg_osreg, impl_id, part_id; + uint32_t qc_subpart_id; retval = dap_dp_init(swjdp); if (retval != ERROR_OK) { @@ -3059,30 +3060,22 @@ static int cortex_a_examine_first(struct target *target) cortex_a->ttypr = ttypr; cortex_a->didr = didr; - /* Unlocking the debug registers */ - if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT == - CORTEX_A15_PARTNUM) { + impl_id = (cpuid & CORTEX_A_MIDR_IMPLEMENTER_MASK) >> CORTEX_A_MIDR_IMPLEMENTER_SHIFT; + part_id = (cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT; + qc_subpart_id = (part_id & CORTEX_A_MIDR_QC_SUBPARTNUM_MASK) >> CORTEX_A_MIDR_QC_SUBPARTNUM_SHIFT; + /* Unlocking the debug registers for various different devices */ + if ((part_id == CORTEX_A15_PARTNUM) + || (part_id == CORTEX_A7_PARTNUM) + || ((impl_id == QUALCOMM_IMPLEMENTER_ID) + && (qc_subpart_id == QUALCOMM_KRAIT_SUBPARTNUM))) { retval = mem_ap_write_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_OSLAR, 0); - if (retval != ERROR_OK) return retval; - } - /* Unlocking the debug registers */ - if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT == - CORTEX_A7_PARTNUM) { - - retval = mem_ap_write_atomic_u32(armv7a->debug_ap, - armv7a->debug_base + CPUDBG_OSLAR, - 0); - if (retval != ERROR_OK) - return retval; - - } retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg); diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h index ea08c67..682acf8 100644 --- a/src/target/cortex_a.h +++ b/src/target/cortex_a.h @@ -38,8 +38,16 @@ #define CORTEX_A8_PARTNUM 0xc08 #define CORTEX_A9_PARTNUM 0xc09 #define CORTEX_A15_PARTNUM 0xc0f + +#define QUALCOMM_IMPLEMENTER_ID 0x51 +#define QUALCOMM_KRAIT_SUBPARTNUM 0x1 + #define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0 #define CORTEX_A_MIDR_PARTNUM_SHIFT 4 +#define CORTEX_A_MIDR_QC_SUBPARTNUM_MASK 0x00000fc0 +#define CORTEX_A_MIDR_QC_SUBPARTNUM_SHIFT 6 +#define CORTEX_A_MIDR_IMPLEMENTER_MASK 0xff000000 +#define CORTEX_A_MIDR_IMPLEMENTER_SHIFT 24 #define CPUDBG_CPUID 0xD00 #define CPUDBG_CTYPR 0xD04 -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
