This is an automated email from Gerrit.
Matthias Welwarsky (matth...@welwarsky.de) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/3813
-- gerrit
commit 1cb06aad08f9b2d3f23b2f543b4d85840d504d90
Author: Matthias Welwarsky <matthias.welwar...@sysgo.com>
Date: Thu Oct 6 16:19:20 2016 +0200
aarch64: allow reading system control register when halted in EL0
There's no access to system control register in EL0. Circumvent by
moving the PE to EL1 before reading, and switch back to original mode
afterwards.
Change-Id: I309f4eea5597ffc88fc892e9bbb826982e8a44ec
Signed-off-by: Matthias Welwarsky <matthias.welwar...@sysgo.com>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 3510db2..41bea2e 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -698,6 +698,8 @@ static int aarch64_post_debug_entry(struct target *target)
switch (armv8->arm.core_mode) {
case ARMV8_64_EL0T:
+ dpmv8_modeswitch(&armv8->dpm, ARMV8_64_EL1T);
+ /* fall through */
case ARMV8_64_EL1T:
case ARMV8_64_EL1H:
retval = armv8->arm.mrs(target, 3, /*op 0*/
@@ -725,13 +727,20 @@ static int aarch64_post_debug_entry(struct target *target)
if (retval != ERROR_OK)
return retval;
break;
- default:
+
+ case ARM_MODE_SVC:
retval = armv8->arm.mrc(target, 15, 0, 0, 1, 0,
&aarch64->system_control_reg);
if (retval != ERROR_OK)
return retval;
break;
+
+ default:
+ LOG_INFO("cannot read system control register in this
mode");
+ break;
}
+ dpmv8_modeswitch(&armv8->dpm, ARM_MODE_ANY);
+
LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
aarch64->system_control_reg_curr = aarch64->system_control_reg;
--
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