This is an automated email from Gerrit.
Matthias Welwarsky (matth...@welwarsky.de) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/3820
-- gerrit
commit 41fd7acbc02d5050eb018b0b0e0b2b94f8297935
Author: Matthias Welwarsky <matthias.welwar...@sysgo.com>
Date: Thu Oct 20 14:46:11 2016 +0200
aarch64: allow reading TTBR register when halted in EL0
There's no access to TTBR in EL0. Circumvent by moving the PE to EL1
before reading, and switch back to original mode afterwards.
Change-Id: I22891b958d3d7e6fad1cb27183c192d975d63d89
Signed-off-by: Matthias Welwarsky <matthias.welwar...@sysgo.com>
diff --git a/src/target/armv8.c b/src/target/armv8.c
index b3c8e68..005e4d8 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -743,6 +743,8 @@ static __unused int armv8_read_ttbcr(struct target *target)
armv8->page_size = (ttbcr >> 14) & 3;
break;
case SYSTEM_CUREL_EL0:
+ armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
+ /* fall through */
case SYSTEM_CUREL_EL1:
retval = dpm->instr_read_data_r0_64(dpm,
ARMV8_MRS(SYSTEM_TCR_EL1, 0),
@@ -770,6 +772,7 @@ static __unused int armv8_read_ttbcr(struct target *target)
LOG_INFO("TTBR0 access above %" PRIx64,
(uint64_t)(armv8->armv8_mmu.ttbr0_mask));
done:
+ armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
dpm->finish(dpm);
return retval;
}
--
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