This is an automated email from Gerrit.
Matthias Welwarsky (matth...@welwarsky.de) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/3817
-- gerrit
commit 3124d9d79be2428de60011e0821afbcd0c90ff17
Author: Matthias Welwarsky <matthias.welwar...@sysgo.com>
Date: Thu Oct 20 13:20:26 2016 +0200
aarch64: cache identification for aarch32 state
Use proper T32 opcodes for cache identification when the PE is in
Aarch32 state
Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d
Signed-off-by: Matthias Welwarsky <matthias.welwar...@sysgo.com>
diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index f496c3c..31e4c79 100644
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -266,17 +266,18 @@ static int armv8_flush_all_data(struct target *target)
static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t
*cache_reg)
{
+ struct armv8_common *armv8 = dpm->arm->arch_info;
int retval = ERROR_OK;
/* select cache level */
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
+ armv8_opcode(armv8, WRITE_REG_CSSELR),
(cl << 1) | (ct == 1 ? 1 : 0));
if (retval != ERROR_OK)
goto done;
retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CCSIDR, 0),
+ armv8_opcode(armv8, READ_REG_CCSIDR),
cache_reg);
done:
return retval;
@@ -319,7 +320,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
goto done;
/* retrieve CTR */
- retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CTR, 0), &ctr);
+ retval = dpm->instr_read_data_r0(dpm,
+ armv8_opcode(armv8, READ_REG_CTR), &ctr);
if (retval != ERROR_OK)
goto done;
@@ -329,7 +331,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
ctr, cache->iminline, cache->dminline);
/* retrieve CLIDR */
- retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CLIDR, 0),
&clidr);
+ retval = dpm->instr_read_data_r0(dpm,
+ armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
if (retval != ERROR_OK)
goto done;
@@ -338,7 +341,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
/* retrieve selected cache for later restore
* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
- retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CSSELR, 0),
&csselr);
+ retval = dpm->instr_read_data_r0(dpm,
+ armv8_opcode(armv8, READ_REG_CSSELR), &csselr);
if (retval != ERROR_OK)
goto done;
@@ -396,7 +400,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
}
/* restore selected cache */
- dpm->instr_write_data_r0(dpm, ARMV8_MSR_GP(SYSTEM_CSSELR, 0), csselr);
+ dpm->instr_write_data_r0(dpm,
+ armv8_opcode(armv8, WRITE_REG_CSSELR), csselr);
if (retval != ERROR_OK)
goto done;
diff --git a/src/target/armv8_opcodes.c b/src/target/armv8_opcodes.c
index 75ea946..2b42cdf 100644
--- a/src/target/armv8_opcodes.c
+++ b/src/target/armv8_opcodes.c
@@ -24,6 +24,7 @@
#include "armv8_opcodes.h"
static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
+ [READ_REG_CTR] = ARMV8_MRS(SYSTEM_CTR, 0),
[READ_REG_CLIDR] = ARMV8_MRS(SYSTEM_CLIDR, 0),
[READ_REG_CSSELR] = ARMV8_MRS(SYSTEM_CSSELR, 0),
[READ_REG_CCSIDR] = ARMV8_MRS(SYSTEM_CCSIDR, 0),
@@ -39,6 +40,7 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
};
static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
+ [READ_REG_CTR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
[READ_REG_CLIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
[READ_REG_CSSELR] = ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
[READ_REG_CCSIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index e57e7e9..b489d57 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -160,6 +160,7 @@
#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
enum armv8_opcode {
+ READ_REG_CTR,
READ_REG_CLIDR,
READ_REG_CSSELR,
READ_REG_CCSIDR,
--
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