This is an automated email from Gerrit. Anonymous Coward ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3955
-- gerrit commit 6511963598052ff8b530c57b05358877d0277f0a Author: Alexander Kurz <[email protected]> Date: Sun Jan 22 11:35:42 2017 +0100 tcl/board: Add config for the Amazon Kindle 3 Add a config to access the Amazon Kindle 3, Model No.D00901. This ebook reader is based on a Freescale i.MX35. The non standard JTAG connector and parts of the reset interface are not present on all boards. Hence, connecting to this JTAG interface requires soldering. Change-Id: I021a3f4804e45d8bdf7f4e34ac548ee93483a5e2 Signed-off-by: Alexander Kurz <[email protected]> diff --git a/tcl/board/kindle3.cfg b/tcl/board/kindle3.cfg new file mode 100644 index 0000000..44b499c --- /dev/null +++ b/tcl/board/kindle3.cfg @@ -0,0 +1,231 @@ +# Board configuration file for Amazon Kindle Model No. D00901 +# using a Freescale MCIMX353DJQ5C i.MX35 processor +# +# Pins: +# TP59-RTCK, TP58-TRSTB, TP57-TMS, TP56-TDO, +# TP55-TDI, TP54-TCK, TP37-DE_B, D14/S4-nSRST +# +# Note: missing D14 and R250 may be replaced by e.g. BAR66 and 33R + +source [find target/imx35.cfg] +source [find target/imx.cfg] + +$_TARGETNAME configure -event reset-init { kindle3_init } +$_TARGETNAME configure -event reset-start { adapter_khz 50 } + +# 128k internal SRAM +$_TARGETNAME configure -work-area-phys 0x10000000 \ + -work-area-size 0x20000 -work-area-backup 0 + +reset_config trst_and_srst separate +jtag_ntrst_assert_width 10 +jtag_ntrst_delay 30 +adapter_nsrst_delay 100 + +# this is broken but enabled by default +arm11 memwrite burst disable + +adapter_khz 100 +ftdi_tdo_sample_edge falling + +proc kindle3_init {} { + imx3x_reset + kindle3_clock_setup + disable_mmu_and_cache + kindle3_misc_init + kindle3_sdram_init + arm core_state arm +} + +proc kindle3_clock_setup {} { + # Core PLL: generate 532MHz from 24MHz CKIH + # BRM0=1, MFD=11, MFI=11, MFN=1 + mww 0x53f8001c 0x800b2c01 + # 300MHz Periph. PLL BRM0=0, MFD=3, MFI=6, MFN=1 + mww 0x53f80020 0x00031801 + # Clock Control: VOL_RDY_CNT=3, ROMW=7, RAMW=7, LPM=1, UPE=1, MPE=1 + mww 0x53f80000 0x003f4208 + + # Post-Divide + mww 0x53f80004 0x00001000 + mww 0x53f80008 0x20000000 + mww 0x53f8000c 0x12020000 + mww 0x53f80010 0x40020202 + mww 0x53f80014 0x21070800 + + adapter_khz 1000 + + # Clock control module (CCM), CGR0-CCGR3 + # Enable clock gating for all targets + mww 0x53f8002c 0xffffffff + mww 0x53f80030 0xffffffff + mww 0x53f80034 0xfbffffff + mww 0x53f80038 0x3f + + # CLKCTL: L2_MEM_VAL to default + mww 0x43f0c010 0x515 + + # COSR: default enable async 32 kHz clock for CKO + mww 0x53f80028 0x7d000020 +} + +proc disable_mmu_and_cache {} { + # Mode Supervisor, disable FIQ, IRQ and imprecise data aborts + reg cpsr 0x1d3 + + # flush entire BTAC + arm mcr 15 0 7 5 6 0 + # invalidate instruction and data cache + # MCR CP15, 0, R1, C7, C7, 0 + arm mcr 15 0 7 7 0 + + # clean and invalidate cache + arm mcr 15 0 7 15 0 + + # disable MMU and caches + arm mcr 15 0 1 0 0 0 + + arm mcr 15 0 15 2 4 0 + + # invalidate TLBs + arm mcr 15 0 8 7 0 0 + + # Drain the write buffer + arm mcr 15 0 7 10 4 0 + + # start from AIPS 2GB region + arm mcr 15 0 15 2 4 0x40000015 +} + +proc kindle3_misc_init { } { + + # AIPS 1 control registers + mww 0x43f00040 0x00000000 + mww 0x43f00044 0x00000000 + mww 0x43f00048 0x00000000 + mww 0x43f0004c 0x00000000 + mww 0x43f00050 0x00000000 + mww 0x43f00000 0x77777777 + mww 0x43f00004 0x77777777 + + # AIPS 2 control registers + mww 0x53f00040 0x00000000 + mww 0x53f00044 0x00000000 + mww 0x53f00048 0x00000000 + mww 0x53f0004c 0x00000000 + mww 0x53f00050 0x00000000 + mww 0x53f00000 0x77777777 + mww 0x53f00004 0x77777777 + + # DQM setup + mww 0x43fac45c 0x00000002 + mww 0x43fac460 0x00000002 + mww 0x43fac464 0x00000002 + mww 0x43fac468 0x00000002 + + mww 0x43fac46c 0x00002002 + mww 0x43fac470 0x00002002 + mww 0x43fac474 0x00002002 + mww 0x43fac478 0x00002002 + mww 0x43fac47c 0x00002002 + mww 0x43fac480 0x00000002 ;# CSD0 + mww 0x43fac484 0x00000002 ;# CSD1 + + mww 0x43fac488 0x00002043 + mww 0x43fac48c 0x00002043 + mww 0x43fac490 0x00000041 + mww 0x43fac494 0x00002082 + mww 0x43fac498 0x00002002 + mww 0x43fac49c 0x00000082 + + mww 0x43fac4a0 0x00002002 + mww 0x43fac4a4 0x00000002 ;# RAS + mww 0x43fac4a8 0x00000002 ;# CAS + mww 0x43fac4ac 0x00000002 ;# SDWE + mww 0x43fac4b0 0x00000002 ;# SDCKE0 + mww 0x43fac4b4 0x00000002 ;# SDCKE1 + mww 0x43fac4b8 0x00000002 ;# SDCLK + + # SDQS0 through SDQS3 + mww 0x43fac4bc 0x00000082 + mww 0x43fac4c0 0x00000082 + mww 0x43fac4c4 0x00000082 + mww 0x43fac4c8 0x00000082 +} + +proc kindle3_sdram_init {} { + #-------------------------------------------- + # Samsung K4X2G323PC-8GD8: 256MB LPDDR1 + #-------------------------------------------- + # IOMUX SD 0 through 31: Keep Enable, Max Drive Strength + mww 0x43fac3dc 0x00000082 + mww 0x43fac3e0 0x00000082 + mww 0x43fac3e4 0x00000082 + mww 0x43fac3e8 0x00000082 + mww 0x43fac3ec 0x00000082 + mww 0x43fac3f0 0x00000082 + mww 0x43fac3f4 0x00000082 + mww 0x43fac3f8 0x00000082 + mww 0x43fac3fc 0x00000082 + mww 0x43fac400 0x00000082 + mww 0x43fac404 0x00000082 + mww 0x43fac408 0x00000082 + mww 0x43fac40c 0x00000082 + mww 0x43fac410 0x00000082 + mww 0x43fac414 0x00000082 + mww 0x43fac418 0x00000082 + mww 0x43fac41c 0x00000082 + mww 0x43fac420 0x00000082 + mww 0x43fac424 0x00000082 + mww 0x43fac428 0x00000082 + mww 0x43fac42c 0x00000082 + mww 0x43fac430 0x00000082 + mww 0x43fac434 0x00000082 + mww 0x43fac438 0x00000082 + mww 0x43fac43c 0x00000082 + mww 0x43fac440 0x00000082 + mww 0x43fac444 0x00000082 + mww 0x43fac448 0x00000082 + mww 0x43fac44c 0x00000082 + mww 0x43fac450 0x00000082 + mww 0x43fac454 0x00000082 + mww 0x43fac458 0x00000082 + + # ESDMISC: trigger local module reset + mww 0xb8001010 0x00000002 + # enable DDR SDRAM device + mww 0xb8001010 0x00000004 + + # ESDCTL0: Enable SDRAM with 14 rows, 10 columns, 32 bits. + # 2x Auto Refresh + mww 0xb8001000 0xa3228080 + mwb 0x80000000 0x0 + mww 0xb8001000 0xa3228080 + mwb 0x80000000 0x0 + + # ESDCFG0: latencies: CAS 3, RAS 7, + # delays: row to column 3, row cycle 16 + mww 0xb8001004 0x0019672f + + # Precharge + mww 0xb8001000 0x93228080 + mww 0x80000400 0x0 + + # Auto-refresh + mww 0xb8001000 0xa3228080 + mwb 0x80000000 0x0 + mwb 0x80000000 0x0 + mwb 0x80000000 0x0 + mwb 0x80000000 0x0 + mwb 0x80000000 0x0 + mwb 0x80000000 0x0 + mwb 0x80000000 0x0 + mwb 0x80000000 0x0 + + # Load mode register + mww 0xb8001000 0xb3228080 + mwb 0x80000033 0x30 + + # Normal read/write + mww 0xb8001000 0x83228080 +} -- ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, SlashDot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
