This is an automated email from Gerrit. Peter Mamonov ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4026
-- gerrit commit 8fcb41fadb3361ef873b168e23466afec585f405 Author: Peter Mamonov <[email protected]> Date: Thu Aug 13 19:53:42 2015 +0400 mips64: do not restore WatchLo/Hi regiters WatchLo/Hi are coupled with hardware breakpoint registers, so don't touch it! Change-Id: I5fe00924e3f390c7086e7ca0fc0bb14ed893510d Signed-off-by: Peter Mamonov <[email protected]> diff --git a/src/target/mips64_pracc.c b/src/target/mips64_pracc.c index 49754fd..e555ce0 100644 --- a/src/target/mips64_pracc.c +++ b/src/target/mips64_pracc.c @@ -831,9 +831,9 @@ int mips64_pracc_write_regs(struct mips_ejtag *ejtag_info, uint64_t *regs) MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 16) * 8, 1), MIPS64_MTC0(2, MIPS64_C0_LLA, 0), MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 17) * 8, 1), - MIPS64_DMTC0(2, MIPS64_C0_WATCHLO, 0), + MIPS64_NOP /*MIPS64_DMTC0(2, MIPS64_C0_WATCHLO, 0)*/, MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 18) * 8, 1), - MIPS64_DMTC0(2, MIPS64_C0_WATCHLO, 1), + MIPS64_NOP /*MIPS64_DMTC0(2, MIPS64_C0_WATCHLO, 1)*/, MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 19) * 8, 1), MIPS64_MTC0(2, MIPS64_C0_WATCHHI, 0), MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 20) * 8, 1), -- ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, SlashDot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
