This is an automated email from Gerrit.

Stafford Horne ([email protected]) just uploaded a new patch set to Gerrit, 
which you can find at http://openocd.zylin.com/4099

-- gerrit

commit 22cb8714f50632c161fd24032d316701ba9c2afb
Author: Stafford Horne <[email protected]>
Date:   Sat Apr 8 15:02:56 2017 +0900

    openrisc: implement multicore registers
    
    These are not yet in the spec but are in the softcore mor1kx and they
    are planned for adding to the spec soon.
    
    Change-Id: Id80303b747ee17982e37162b28cb6a27b06cf091
    Signed-off-by: Stafford Horne <[email protected]>

diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index ed62f8c..ce47634 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -155,6 +155,8 @@ static const struct or1k_core_reg_init or1k_init_reg_list[] 
= {
        {"esr13"    , GROUP0 + 77,   "org.gnu.gdb.or1k.group0", "system"},
        {"esr14"    , GROUP0 + 78,   "org.gnu.gdb.or1k.group0", "system"},
        {"esr15"    , GROUP0 + 79,   "org.gnu.gdb.or1k.group0", "system"},
+       {"coreid"   , GROUP0 + 128,  "org.gnu.gdb.or1k.group0", "system"},
+       {"numcores" , GROUP0 + 129,  "org.gnu.gdb.or1k.group0", "system"},
 
        {"dmmuucr"  , GROUP1 + 0,    "org.gnu.gdb.or1k.group1", "dmmu"},
        {"dmmuupr"  , GROUP1 + 1,    "org.gnu.gdb.or1k.group1", "dmmu"},

-- 

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