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** [tickets:#150] Targets in "Examine Deferred" state create issues**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Apr 21, 2017 09:09 AM UTC by Pierre
**Last Updated:** Fri Apr 21, 2017 09:09 AM UTC
**Owner:** nobody
**Attachments:**
-
[single-stepping.txt](https://sourceforge.net/p/openocd/tickets/150/attachment/single-stepping.txt)
(5.2 kB; text/plain)
Hi,
First of all thanks for making openocd, it's a great project!
I'm using the git version of openocd 0.10.0+dev-00096-gf605a23bc (cloned
yesterday).
I'm targeting a Lemaker HiKey board which has a hi6220 (8 cores). If I'm
correct, at reset only core 0 is powered which means that cores 1-7 can't be
examined, that's why -defer-examine is used in
https://github.com/ntfreak/openocd/blob/master/tcl/target/hi6220.cfg#L34
I'm debugging code in early stages of the boot when cores 1-7 aren't powered
yet and thus not examined yet and having unexamined targets creates issues with
openocd, for example:
* setting a breakpoint generates an error because openocd tries to do it on
every target (even unexamined ones)
~~~
> bp 0x10000000 4 hw
no hardware breakpoint available
can't add breakpoint: resource not available
Failure setting breakpoint, the same address(IVA) is already used
> bp
Breakpoint(IVA): 0x10000000, 0x4, 1
~~~
* single-stepping an instruction in gdb "si" generates a segfault in openocd.
I'm attaching a backtrace
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I made 2 quick fixes which solve my problems
https://github.com/piec/openocd/commits/b91b50c3bd56783525c60393b282115e4bd80f9d
I think the stepping fix is ok.
But the breakpoint commit is just a workaround, I suppose openocd should save
the breakpoints to be added after defered targets are examined (later).
Best regards,
Pierre
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