This is an automated email from Gerrit. Paul Fertser ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4151
-- gerrit commit 66b3d1f55603effe767e072d87ed074555af1115 Author: Paul Fertser <[email protected]> Date: Wed May 31 16:57:34 2017 +0300 flash: nor: ath79: fix build failure due to recent MIPS changes Change-Id: I7139b0658f048afea2d16216c93e8946356a630d Signed-off-by: Paul Fertser <[email protected]> diff --git a/src/flash/nor/ath79.c b/src/flash/nor/ath79.c index 0543085..6889b4a 100644 --- a/src/flash/nor/ath79.c +++ b/src/flash/nor/ath79.c @@ -136,9 +136,9 @@ static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info, const uint32_t preamble1[] = { /* $15 = MIPS32_PRACC_BASE_ADDR */ - MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR), + MIPS32_LUI(0, 15, PRACC_UPPER_BASE_ADDR), /* $1 = io_base */ - MIPS32_LUI(1, UPPER16(io_base)), + MIPS32_LUI(0, 1, UPPER16(io_base)), }; ath79_pracc_addn(ctx, preamble1, ARRAY_SIZE(preamble1)); if (ath79_info->spi.pre_deselect) { @@ -148,31 +148,31 @@ static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info, ath79_info->spi.pre_deselect = 0; const uint32_t pre_deselect[] = { /* [$1 + FS] = 1 (enable flash io register access) */ - MIPS32_LUI(2, UPPER16(1)), - MIPS32_ORI(2, 2, LOWER16(1)), - MIPS32_SW(2, ATH79_REG_FS, 1), + MIPS32_LUI(0, 2, UPPER16(1)), + MIPS32_ORI(0, 2, 2, LOWER16(1)), + MIPS32_SW(0, 22, ATH79_REG_FS, 1), /* deselect flash just in case */ /* $2 = SPI_CS_DIS */ - MIPS32_LUI(2, UPPER16(cs_high)), - MIPS32_ORI(2, 2, LOWER16(cs_high)), + MIPS32_LUI(0, 22, UPPER16(cs_high)), + MIPS32_ORI(0, 22, 2, LOWER16(cs_high)), /* [$1 + WRITE] = $2 */ - MIPS32_SW(2, ATH79_REG_WRITE, 1), + MIPS32_SW(0, 22, ATH79_REG_WRITE, 1), }; ath79_pracc_addn(ctx, pre_deselect, ARRAY_SIZE(pre_deselect)); } const uint32_t preamble2[] = { /* t0 = CLOCK_LOW + 0-bit */ - MIPS32_LUI(8, UPPER16((clock_low + 0))), - MIPS32_ORI(8, 8, LOWER16((clock_low + 0))), + MIPS32_LUI(0, 28, UPPER16((clock_low + 0))), + MIPS32_ORI(0, 28, 8, LOWER16((clock_low + 0))), /* t1 = CLOCK_LOW + 1-bit */ - MIPS32_LUI(9, UPPER16((clock_low + 1))), - MIPS32_ORI(9, 9, LOWER16((clock_low + 1))), + MIPS32_LUI(0, 29, UPPER16((clock_low + 1))), + MIPS32_ORI(0, 29, 9, LOWER16((clock_low + 1))), /* t2 = CLOCK_HIGH + 0-bit */ - MIPS32_LUI(10, UPPER16((clock_high + 0))), - MIPS32_ORI(10, 10, LOWER16((clock_high + 0))), + MIPS32_LUI(0, 210, UPPER16((clock_high + 0))), + MIPS32_ORI(0, 210, 10, LOWER16((clock_high + 0))), /* t3 = CLOCK_HIGH + 1-bit */ - MIPS32_LUI(11, UPPER16((clock_high + 1))), - MIPS32_ORI(11, 11, LOWER16((clock_high + 1))), + MIPS32_LUI(0, 211, UPPER16((clock_high + 1))), + MIPS32_ORI(0, 211, 11, LOWER16((clock_high + 1))), }; ath79_pracc_addn(ctx, preamble2, ARRAY_SIZE(preamble2)); @@ -186,58 +186,58 @@ static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info, if (bit) { /* [$1 + WRITE] = t1 */ pracc_add(ctx, 0, - MIPS32_SW(9, ATH79_REG_WRITE, 1)); + MIPS32_SW(0, 29, ATH79_REG_WRITE, 1)); /* [$1 + WRITE] = t3 */ pracc_add(ctx, 0, - MIPS32_SW(11, ATH79_REG_WRITE, 1)); + MIPS32_SW(0, 211, ATH79_REG_WRITE, 1)); } else { /* [$1 + WRITE] = t0 */ pracc_add(ctx, 0, - MIPS32_SW(8, ATH79_REG_WRITE, 1)); + MIPS32_SW(0, 28, ATH79_REG_WRITE, 1)); /* [$1 + WRITE] = t2 */ pracc_add(ctx, 0, - MIPS32_SW(10, ATH79_REG_WRITE, 1)); + MIPS32_SW(0, 210, ATH79_REG_WRITE, 1)); } } if (i % 4 == 3) { /* $3 = [$1 + DATA] */ - pracc_add(ctx, 0, MIPS32_LW(3, ATH79_REG_DATA, 1)); + pracc_add(ctx, 0, MIPS32_LW(0, 23, ATH79_REG_DATA, 1)); /* [OUTi] = $3 */ pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + pracc_out, - MIPS32_SW(3, PRACC_OUT_OFFSET + + MIPS32_SW(0, 23, PRACC_OUT_OFFSET + pracc_out, 15)); pracc_out += 4; } } if (len & 3) { /* not a multiple of 4 bytes */ /* $3 = [$1 + DATA] */ - pracc_add(ctx, 0, MIPS32_LW(3, ATH79_REG_DATA, 1)); + pracc_add(ctx, 0, MIPS32_LW(0, 23, ATH79_REG_DATA, 1)); /* [OUTi] = $3 */ pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + pracc_out, - MIPS32_SW(3, PRACC_OUT_OFFSET + pracc_out, 15)); + MIPS32_SW(0, 23, PRACC_OUT_OFFSET + pracc_out, 15)); pracc_out += 4; } if (ath79_info->spi.post_deselect && !partial_xfer) { const uint32_t post_deselect[] = { /* $2 = SPI_CS_DIS */ - MIPS32_LUI(2, UPPER16(cs_high)), - MIPS32_ORI(2, 2, LOWER16(cs_high)), + MIPS32_LUI(0, 22, UPPER16(cs_high)), + MIPS32_ORI(0, 22, 2, LOWER16(cs_high)), /* [$1 + WRITE] = $2 */ - MIPS32_SW(2, ATH79_REG_WRITE, 1), + MIPS32_SW(0, 22, ATH79_REG_WRITE, 1), /* [$1 + FS] = 0 (disable flash io register access) */ - MIPS32_XORI(2, 2, 0), - MIPS32_SW(2, ATH79_REG_FS, 1), + MIPS32_XORI(0, 22, 2, 0), + MIPS32_SW(0, 22, ATH79_REG_FS, 1), }; ath79_pracc_addn(ctx, post_deselect, ARRAY_SIZE(post_deselect)); } /* common pracc epilogue */ /* jump to start */ - pracc_add(ctx, 0, MIPS32_B(NEG16(ctx->code_count + 1))); + pracc_add(ctx, 0, MIPS32_B(0, NEG16(ctx->code_count + 1))); /* restore $15 from DeSave */ - pracc_add(ctx, 0, MIPS32_MFC0(15, 31, 0)); + pracc_add(ctx, 0, MIPS32_MFC0(0, 15, 31, 0)); return pracc_out / 4; } @@ -289,7 +289,7 @@ static int ath79_spi_bitbang_chunk(struct flash_bank *bank, LOG_DEBUG("Assembled %d instructions, %d stores", ctx.code_count, ctx.store_count); - ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, out); + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, out, 1); if (ctx.retval != ERROR_OK) goto exit; -- ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
