This is an automated email from Gerrit. Tomas Vanek ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4287
-- gerrit commit db8f17749c3fb2a46457d5791d923460f194cf71 Author: Tomas Vanek <[email protected]> Date: Thu Nov 2 13:01:45 2017 +0100 target/cortex_a: convert assert_reset to reset_prepare_trigger [WIP] Also contains a modified imx6.cfg for testing Change-Id: I77d4cabbef5801578b97eff73a4ef2eb761e382e Signed-off-by: Tomas Vanek <[email protected]> diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 5d90e34..c1f6491 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1852,6 +1852,19 @@ static int cortex_a_remove_breakpoint(struct target *target, struct breakpoint * * Cortex-A Reset functions */ +static int cortex_a_reset_clear_internal_state(struct target *target) +{ + struct armv7a_common *armv7a = target_to_armv7a(target); + + /* registers are now invalid */ + if (target_was_examined(target)) + register_cache_invalidate(armv7a->arm.core_cache); + + target->state = TARGET_RESET; + + return ERROR_OK; +} +#if 0 static int cortex_a_assert_reset(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); @@ -1922,6 +1935,7 @@ static int cortex_a_deassert_reset(struct target *target) return ERROR_OK; } +#endif static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t *dscr) { @@ -3440,8 +3454,10 @@ struct target_type cortexa_target = { .resume = cortex_a_resume, .step = cortex_a_step, - .assert_reset = cortex_a_assert_reset, - .deassert_reset = cortex_a_deassert_reset, + .reset_clear_internal_state = cortex_a_reset_clear_internal_state, +/* .reset_prepare_trigger = cortex_a_reset_prepare_trigger,*/ +/* .assert_reset = cortex_a_assert_reset,*/ +/* .deassert_reset = cortex_a_deassert_reset,*/ /* REVISIT allow exporting VFP3 registers ... */ .get_gdb_reg_list = arm_get_gdb_reg_list, @@ -3528,8 +3544,10 @@ struct target_type cortexr4_target = { .resume = cortex_a_resume, .step = cortex_a_step, - .assert_reset = cortex_a_assert_reset, - .deassert_reset = cortex_a_deassert_reset, + .reset_clear_internal_state = cortex_a_reset_clear_internal_state, +/* .reset_prepare_trigger = cortex_a_reset_prepare_trigger,*/ +/* .assert_reset = cortex_a_assert_reset,*/ +/* .deassert_reset = cortex_a_deassert_reset,*/ /* REVISIT allow exporting VFP3 registers ... */ .get_gdb_reg_list = arm_get_gdb_reg_list, diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg index 4f7e98a..ff03040 100644 --- a/tcl/target/imx6.cfg +++ b/tcl/target/imx6.cfg @@ -6,6 +6,12 @@ if { [info exists CHIPNAME] } { set _CHIPNAME imx6 } +if { [info exists SMP] } { + set _SMP $SMP +} else { + set _SMP 4 +} + # CoreSight Debug Access Port if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID @@ -39,21 +45,51 @@ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ # core 1 - 0x82152000 # core 2 - 0x82154000 # core 3 - 0x82156000 -set _TARGETNAME $_CHIPNAME.cpu.0 -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 cortex_a -chain-position $_CHIPNAME.dap \ -coreid 0 -dbgbase 0x82150000 +set _CORES $_TARGETNAME.0 + +if { $_SMP >= 2 } { + target create $_TARGETNAME.1 cortex_a -chain-position $_CHIPNAME.dap \ + -coreid 1 -dbgbase 0x82152000 -defer-examine +} +if { $_SMP == 2 } { + set _CORES [list $_TARGETNAME.1 $_TARGETNAME.0] + target smp {*}$_CORES +} +if { $_SMP == 4 } { + target create $_TARGETNAME.2 cortex_a -chain-position $_CHIPNAME.dap \ + -coreid 2 -dbgbase 0x82154000 -defer-examine + target create $_TARGETNAME.3 cortex_a -chain-position $_CHIPNAME.dap \ + -coreid 3 -dbgbase 0x82156000 -defer-examine + + set _CORES [list $_TARGETNAME.3 $_TARGETNAME.2 \ + $_TARGETNAME.1 $_TARGETNAME.0 ] + target smp {*}$_CORES +} + # some TCK cycles are required to activate the DEBUG power domain jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" -proc imx6_dbginit {target} { - # General Cortex-A8/A9 debug initialisation - cortex_a dbginit +# Halt after 'reset halt'. Some code is executed before halt. +proc do_halt { t } { + global arp_reset_halting + if { $arp_reset_halting && [arp_is_tap_enabled $t] + && [$t was_examined] } { + $t arp_poll + if { [$t curstate] eq "running" } { + echo "$t: ran after reset and before halt..." + $t arp_halt + } + } } -# Slow speed to be sure it will work -adapter_khz 1000 -$_TARGETNAME configure -event reset-start { adapter_khz 1000 } - -$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME" -$_TARGETNAME configure -event gdb-attach { halt } +foreach t $_CORES { + set_debug_under_reset $t cleared + $t configure -event reset-deassert-post \ + "arp_default_reset_deassert_post $t + do_halt $t" + $t configure -event gdb-attach { halt } +} -- ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
